5AGZME5H2F35C3N Altera Corporation, 5AGZME5H2F35C3N Datasheet
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5AGZME5H2F35C3N
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5AGZME5H2F35C3N Summary of contents
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www ...
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... High-performance FPGA fabric Internal memory blocks Altera Corporation TSMC's 28-nm process technology: Arria V GX, GT, SX, and ST—28-nm low power (28LP) process Arria V GZ—28-nm high performance (28HP) process Lowest static power in its class (less than 1.2 W for 500K logic elements (LEs) at 85°C junction under typical conditions) 0 ...
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... LC oscillator ATX transmitter PLLs (Arria V GZ only) 1.6 Gbps LVDS receiver and transmitter 800 MHz/1.6 Gbps external memory interface On-chip termination (OCT) 1 3.3 V support . CCIO Arria V Device Overview Description ® ® (PCIe ) Gen2 (x1, x2, or x4) and Gen1 (x1, x2, ® (SRIO) PCS 3 Altera Corporation ...
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... HPS (Arria V SX and ST devices only) Configuration Altera Corporation Hard memory controller-up to 1.066 Gbps Soft memory controller-up to 1.6 Gbps 600 Mbps to 12.5 Gbps integrated transceiver speed Less than 105 mW per channel at 6 Gbps, less than 165 mW per channel at 10 Gbps, and less than 170 mW per channel at 12.5 Gbps ...
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... F : FineLine BGA (FBGA) Operating Temperature C : Commercial (T = 0° 85° Industrial (T = -40° 100° Optional Suffix Indicates specific device options or shipment method N : Lead-free packaging ES : Engineering sample FPGA Fabric Speed Grade 3 (fastest Altera Corporation ...
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... For the number of LVDS channels in each package, refer to the in Arria V Devices chapter the F896 package, the PCIe hard IP block on the right side of the Arria V GX A5, A7, B1, and B3 devices support x1 for Gen1 and Gen2 data rates. Altera Corporation 156 ...
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... Package Code options or shipment method 27 : 672 pins N : Lead-free packaging 31 : 896 pins ES : Engineering sample 35 : 1,152 pins FPGA Fabric 40 : 1,517 pins Speed Grade 3 (fastest) 5 Member Code C7 D3 242 362 91,680 136,880 366,720 547,520 7 F1517 (40 mm) XCVR — 504 190,240 760,960 Altera Corporation ...
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... Chip-to-chip connections only. For information about 10 Gbps SFF-8431 compliance, contact Altera. 9 The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. 10 For the number of LVDS channels in each package, refer to the in Arria V Devices chapter. Altera Corporation C3 M10K 10,510 MLAB 961 396 792 ...
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... L : Low-power device 40 : 1,517 pins FPGA Fabric Speed Grade 3 (fastest) 4 Member Code E3 E5 360 400 135,840 150,960 543,360 603,840 19,140 28,800 4,245 4,718 1,044 1,092 2,088 2,184 414 674 9 E7 450 169,800 679,200 34,000 5,306 1,139 2,278 24 36 674 Altera Corporation ...
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... Family Signature 5A : Arria V Family Variant SX : SoC FPGA with 6-Gbps transceivers Member Code B3 : 350K logic elements B5 : 462K logic elements 13 For the number of LVDS channels in each package, refer to the in Arria V Devices chapter. Altera Corporation E1 99 108 1 H780 F1152 (29 mm) (35 mm) XCVR GPIO 12 ...
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... Dual-core F1152 F1517 (40 mm) XCVR FPGA HPS I/O GPIO 210 18 540 210 18 540 High-Speed Differential I/O Interfaces and DPA 11 B5 462 174,340 697,360 22,820 2,658 1,068 2,136 528 216 120 136 Dual-core XCVR 210 30 210 30 Altera Corporation ...
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... FPGA PLL HPS PLL Transceiver 17 The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs. 18 Chip-to-chip connections only. For information about 10 Gbps SFF-8431 compliance, contact Altera. Altera Corporation Transceiver Count Package Type Maximum channels F : FineLine BGA (FBGA ...
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... Member Code D3 540 210 120 136 Dual-core Dual-core F1517 (40 mm) XCVR FPGA HPS I/O 6 Gbps 10 GPIO Gbps 18 8 540 210 18 8 540 210 High-Speed Differential I/O Interfaces and DPA 13 D5 540 210 120 136 XCVR 6 Gbps 10 Gbps Altera Corporation ...
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... Arria V devices use ALM as the basic building block of the logic fabric. The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than previous generations. Altera Corporation Member Code F672 ...
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... Adaptive 5 LUT Full Adder Embedded Memory Capacity in Arria V Devices Multiplier Size (Bit) Three Two Two with accumulate One Arria V Device Overview Reg Reg Reg Reg on page standalone-17. DSP Block Resource Altera Corporation ...
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... GZ E5 1,092 E7 1,139 B3 809 Arria 1,068 D3 809 Arria 1,068 Altera Corporation Multiplier Size (Bit) One Independent Input and Output Multiplications Operator Multi Mul Mul- plier tiplier tiplier 720 480 240 1,188 792 396 1,800 1,200 ...
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... Altera Corporation 17 Total RAM Bit (Kb) 8,463 11,471 12,973 15,108 16,952 19,358 23,072 27,046 11,471 15,108 19,358 27,046 14,294 23,385 33,518 39,306 ...
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... Altera's global, quadrant, and peripheral clock structure. This clock structure is supported by dedicated clock input pins and fractional PLLs. Note: To reduce power consumption, the Quartus II software identifies all unused sections of the clock network and powers them down. Altera Corporation M20K M10K Block RAM Bit ...
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... Arria V devices contain PCIe hard IP that is designed for performance, ease-of-use, and increased functionality. The PCIe hard IP consists of the MAC, data link, and transaction layers. Arria V Device Overview OCT) for all I/O banks with OCT calibration to limit the termination T 19 Arria V Device Overview ) and programmable OD Altera Corporation ...
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... II+, QDR II, and DDR II+ SRAM devices, and RLDRAM II devices for maximum flexibility. Note: DDR3 SDRAM leveling is supported only in Arria V GZ devices. External Memory Performance Table 18: External Memory Interface Performance in Arria V Devices Interface DDR3 SDRAM DDR2 SDRAM Altera Corporation FPGA Device Host CPU PCIe Link Root Complex Local Local ...
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... Arria V Device Overview Soft Controller (MHz) Arria V GX, GT, SX, and Arria 400 — 400 400 400 400 400 400 400 400 HPS Hard Controller (MHz) 533 533 400 400 333 Altera Corporation 21 — 667 533 533 500 500 333 333 — — ...
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... The following figures are graphical representations of a top view of the silicon die, which corresponds to a reverse view for flip chip packages. Different Arria V devices may have different floorplans than the ones shown in the figures. Figure 9: Device Chip Overview for Arria V GX and GT Devices Altera Corporation I/O, LVDS, and Memory Interface Hard Memory Controller Hard Memory Controller ...
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... Core Logic Fabric and MLABs M20K Internal Memory Blocks Variable-Precision DSP Blocks Hard Transceiver PCS PMA Hard Transceiver PCS PMA Hard Transceiver PCS PMA Transceiver Individual Channels Distributed Memory Core Logic Fabric and MLABs M10K Internal Memory Blocks Variable-Precision DSP Blocks Altera Corporation ...
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... Gbps to 10.3125 Gbps—supported through dedicated bit interface that bypass the PCS hard IP and connects the PMA directly to the core logic. In Arria V GZ, this is supported in the transceiver PCS hard IP. Altera Corporation Capability Arria V GX, GT, SX, and ST devices—Driving capability at 6.5536 Gbps with channel loss Arria V GZ devices— ...
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... Phase compensation FIFO Rate match FIFO Word aligner 8B/10B decoder Byte deserializer Phase compensation FIFO XAUI state machine for realigning four channels Deskew FIFO circuitry Byte deserializer Phase compensation FIFO Word aligner 8B/10B decoder Byte deserializer Phase compensation FIFO RX deterministic latency Altera Corporation ...
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... Table 22: Transceiver PCS Features for Arria V GZ Devices Protocol Custom PHY GPON Custom 10G PHY PCIe Gen1 (x1, x4, x8) PCIe Gen2 (x1, x4, x8) PCIe Gen3 (x1, x4, x8) 10GbE Interlaken Altera Corporation Data Rates Transmitter Data Path Features (Gbps) 0.6 to 9.80 Phase compensation FIFO 1.25 and 2.5 Byte serializer 8B/10B encoder Bit-slip Channel bonding 9.98 to 12.5 TX FIFO ...
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... Word aligner Deskew FIFO Rate match FIFO 8B/10B decoder Byte deserializer Byte ordering XAUI state machine for realigning four channels Word aligner Deskew FIFO Rate match FIFO 8B/10B decoder Byte deserializer Byte ordering SRIO V2.1-compliant x2 and x4 deskew state machine Altera Corporation ...
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... DMA controller. For modules without an integrated DMA controller, an additional DMA controller module provides up to eight channels of high-bandwidth data transfers. Peripherals that communicate off-chip are multiplexed with other peripherals at the HPS pin level. This allows you to choose which peripherals to interface with other devices on your PCB. Altera Corporation Lightweight FPGA-to-HPS HPS-to-FPGA ...
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... Although the FPGA fabric and HPS are on separate power domains, the HPS must remain powered up during operation while the FPGA fabric can be powered up or down as required. Arria V Device Overview ™ ) specifications, consist of the following bridges: 29 Arria V Device Overview ® ) Advanced ® Altera Corporation ...
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... Partial reconfiguration is supported through the FPP x16 configuration interface. You can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfiguration of both the device core and transceivers. Altera Corporation ® , and other operating systems will be available for the SoC FPGAs. For more information Altera sales team ...
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... Yes — Yes Yes — Yes Yes — 29 Yes Yes Yes Yes Yes — Yes Yes Yes — — — 29 Yes Yes Yes Yes Yes — Altera Corporation 31 Remote System Update Yes — Parallel flash loader — — Parallel flash loader ...
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... November 2012 2012.11.19 October 2012 July 2012 June 2012 Altera Corporation Version Added the L optional suffix to the Arria V GZ ordering code for the -I3 speed grade. Added a note about the power-up sequence requirement if you plan to migrate your design from the Arria and A7, and Arria devices to other Arria V devices ...
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... Table 1–9, and Table 1–10. Added “SoC FPGA with HPS” section. Updated “Clock Networks and PLL Clock Sources” and “Ordering Information” sections. Updated Figure 1–5. Added Figure 1–6. Minor text edits. 1.0 Initial release. Arria V Device Overview Changes Altera Corporation 33 ...