LFE2-6E-5F256I Lattice, LFE2-6E-5F256I Datasheet - Page 73

• Manufacturer Part Number: LFE2-6E-5F256I
• Description: FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -5 I
• Manufacturer: Lattice

Specifications of LFE2-6E-5F256I

• Number Of I/os: 190
• Maximum Operating Frequency: 311 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-256
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 450

Lattice Semiconductor
sysCLOCK SPLL Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v.
Parameter
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
PA
IPJIT
FBKDLY
HI
LO
RST
4
2
1
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
Reset Signal Pulse Width (RESETM/
RESETK)
Reset Signal Pulse Width (CNTRST)
Reset Signal Pulse Width (CNTRST)
LOCK
Description
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Default Duty Cycle Selected
f
f
N/M = Integer
At 90% or 10%
Without external capacitor
With external capacitor
90% to 90%
10% to 10%
Without external capacitor
With external capacitor
OUT
OUT
3-26
> 100 MHz
< 100 MHz
Conditions
DC and Switching Characteristics
LatticeECP2 Family Data Sheet
3
Min.
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
420
420
840
—
—
Units
UIPP
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ns
µs
µs
ps
ps
ns
ns
ns
ns
ns
ns
%