LFE2-6E-5F256I Lattice, LFE2-6E-5F256I Datasheet - Page 18

• Manufacturer Part Number: LFE2-6E-5F256I
• Description: FPGA - Field Programmable Gate Array 6K LUTs 190 I/O DSP 1.2V -5 I
• Manufacturer: Lattice

Specifications of LFE2-6E-5F256I

• Number Of I/os: 190
• Maximum Operating Frequency: 311 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-256
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 450

Lattice Semiconductor
Figure 2-13. Secondary Clock Regions ECP2-50
Figure 2-14. Per Region Secondary Clock Selection
Slice Clock Selection
Figure 2-15 shows the clock selections and Figure 2-16 shows the control selections for Slice0 through Slice2. All
the primary clocks and the four secondary clocks are routed to this clock selection mux. Other signals via routing
can be used as a clock input to the slices. Slice controls are generated from the secondary clocks or other signals
connected via routing.
SC0
24:1
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
I/O Bank 0
I/O Bank 5
Region 1
SC1
Region 2
Region 3
Region 4
24:1
Control
Secondary Clock Feedlines: 8 PIOs + 16 Routing
8 Secondary Clocks (SC0 to SC7) per Quadrant
SC2
24:1
SC3
24:1
SC4
2-15
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
24:1
Region 5
I/O Bank 1
Region 6
Region 7
Region 8
I/O Bank 4
SC5
24:1
Clock
SC6
24:1
LatticeECP2 Family Data Sheet
SC7
24:1
Vertical Routing
Channel Regional
Boundary
DSP Row
Regional
Boundary
DSP Row
Regional
Boundary
EBR Row
Regional
Boundary
Architecture