PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 25

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
PCI Configuration Using Core Configuration Space Port
A set of signals called the Configuration Space Port is provided at the local bus side of the core to allow the user to
define the PCI configuration space as required for the user’s system. The names of these Core configuration input
signals are all suffixed with _p.
Appropriate parameter values are to be assigned to the designated input signals of Core configuration space port
to implement the desired PCI configuration space. Here are two examples to achieve this:
1. Directly assign parameter values to the input signals of Core configuration space port. The user needs to pro-
2. Typically, two Verilog files, para_cfg.v and PCI_params.v, can be used to load these parameters to Core’s Con-
Table 2-9. IPexpress Parameters for PCI IP Core
Local Address Bus Width
1. The value for PCI Data Bus size is set in each eval configuration as described in the appendices of the PCI IP core data sheet.
2. For 32-bit PCI Data Bus, only 32-bit Local Data Bus sizes are supported. For 64-bit PCI Data Bus, only 64-bit Local Data Bus sizes 
are supported.
vide hard coded values to the Core‘s Configuration Space Port input signals in the core instantiation.
module pci_top();
endmodule
figuration Space Port. These files are available in Lattice PCI IP release package.
• Edit the PCI_params.v to set correct values to the parameters. Parameter names in PCI_params.v are all suf-
• Instantiate para_cfg module and appropriately connect its ports to the Core configuration input signals of PCI
para_cfg module will load the parameters, defined in PCI_params.v, into the Core’s Configuration Space Port
input signals.
module pci_top();
fixed with _g. Alternatively use the PCI GUI provided with Lattice’s software design tools to generate the
PCI_params.v. Refer the note given below.
IP core.
…
customer_design
pci_core
…
wire
wire
…
…
Parameter Name
[15:0]
[ 1:0]
.xxxx(xxxx),
.yyyy(yyyy),
…………….
.zzzz(zzzz)
;
…
.vdr_id_p(16’h1234),
…
.dev_tim_p(2’b10),
…
);
core_inst( .framen(framen),
vdr_id;
dev_tim;
cus_design _inst(
32- or 64-bit
Range
25
//vendor_id = 16’h1234
//devsel_timing = 2’b10
Functional Description
PCI IP Core User’s Guide
Default(s)
(slow)
32-bit