PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 125

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
IPUG18_09.2, November 2010
Figure 2-44. 32-bit Target Disconnect with Data for Read Transaction
Table 2-50. 32-bit Target Disconnect with Data for Read Transaction
CLK
4
5
6
7
lt_disconnectn
lt_addressout
lt_data_xfern
l_ad_in[31:0]
bar_hit[5:0]
cben[3:0]
The devseln signal is driven low to indicate that the PCI IP core is selected for the transaction. The lt_rdyn
signal is driven low to indicate that the back-end application is ready to provide data on the next clock cycle.
Because the target cannot complete any more PCI data phases, the lt_disconnectn signal is also driven
low.
The lt_data_xfern signal is driven low by the PCI IP core to the back-end to indicate that data in available on
l_ad_in.
The trdyn and stopn signals are driven low because both lt_rdyn and lt_disconnectn were driven low
during the previous two clock cycles. The lt_data_xfern signal is de-asserted because lt_rdyn was de-
asserted during the previous cycle.Data 1 is presented on the PCI bus via ad[31:0]
The PCI master de-asserts framen to acknowledge the disconnection initiated by the target.The PCI IP core
de-asserts trdyn since the completion of the last PCI data phase and the assertion of stopn.
ad[31:0]
devseln
lt_r_nw
framen
lt_rdyn
stopn
trdyn
irdyn
par
clk
1
Don’t care
Command
Address
Bus
0x00
2
Address
Parity
Don’t care
3
4
Don’t care
Enable 1
Byte
Data Parity 1
125
5
Description
Data 1
6
Address
0x01
Data 1
7
Data Parity
Don’t care
Don’t care
1
Don’t care
8
Functional Description
Don’t care
PCI IP Core User’s Guide
9
0x00
10