PCI-MT32-O4-N2 Lattice, PCI-MT32-O4-N2 Datasheet - Page 22

• Manufacturer Part Number: PCI-MT32-O4-N2
• Description: FPGA - Field Programmable Gate Array PCI Master/Target 32B
• Manufacturer: Lattice

Specifications of PCI-MT32-O4-N2

• Factory Pack Quantity: 1

Lattice Semiconductor
Table 2-6. Status Register Descriptions (Continued)
Table 2-7. Memory Base Address Register
IPUG18_09.2, November 2010
Base Address Registers
The PCI IP core supports up to six Base Address Registers (BARs) for Master/Target and Target configurations.
The BAR holds the base address for the PCI IP core, and it is used to point to the starting address of the PCI IP
core in the system memory map. They are configured differently based on whether they are mapped in memory or
I/O space. A memory location is addressed using 32 bits or 64 bits while I/O locations are limited to 32-bit
addresses. The six BARs consist of 192 bits in the Configuration Space and are located in address locations 0x10
to 0x27.
BAR Mapped to Memory Space
When selecting the amount of required memory for a BAR, the amount of memory is saved to the BAR0-BAR5
parameters in its 2’s complement form. Bits 0 through 3 of a memory BAR describes the attributes of the BAR and
do not change. The minimum recommended amount of memory a BAR should request is 4Kbytes.
Table 2-7
Figure 2-5. Memory Base Address Register
SERR Enable is used to enable the serrn driver. To enable, this bit is set to a 1. After reset this bit is set to 0.
Location
Location
0,1,2,3,6
4-31/63
Bit
1-2
13
14
15
Bit
0
3
describe the configuration of a BAR for memory space.
Received Master Abort is set to a 1 by the Core after it terminates a cycle with a master abort with the exception
of special cycles.
Signaled System Error with serrn is set when the device asserts serrn. Writing a one clears the bit.
Detected Parity Error is used to indicate a parity error even if the parity error handling is disabled.
Reserved Bits The returned value for each of these bits is 0 when this register is read.
Memory/I/O Space Indicator indicates whether the base address is mapped to I/O or memory space. A 0 indi-
cates mapping to the memory space. The value of this bit is set by bit 0 of the BAR0-BAR5 parameters.
Base Address Type is used to determine whether the BAR is mapped into a 32-bit or 64-bit address space.
These bits have the following meaning:
00 - located in 32-bit address space
01 - reserved
10 - located in 64-bit address space
11 - reserved
Prefetchable Enable is determined by bit 3. It is a read-only bit that indicates if the memory space is prefetchable.
A value of 1 means the memory space is prefetchable. Bit 3 of the BAR0-BAR5 parameters sets the value of this
bit.
Bits 4-31/63 are read/write to hold memory address and are initialized by the BAR0-BAR5 parameters.
31/63
Prefechable Enable
Base Address Type
Memory/IO Space Indicator
22
Description
Description
4
3
2
1
Functional Description
0
PCI IP Core User’s Guide
Figure 2-5
and