LCMXO2-4000ZE-1FG484C Lattice, LCMXO2-4000ZE-1FG484C Datasheet - Page 47
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LCMXO2-4000ZE-1FG484C
Manufacturer Part Number
LCMXO2-4000ZE-1FG484C
Description
FPGA - Field Programmable Gate Array 4320 LUTs 279 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000ZE-1FG484C
Rohs
yes
Number Of Gates
4 K
Embedded Block Ram - Ebr
92 Kbit
Number Of I/os
279
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 1.26 V, 1.14 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
fpBGA-484
Distributed Ram
34 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
124 uA
Factory Pack Quantity
60
User Flash Memory - Ufm
96 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000ZE-1FG484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
sysIO Single-Ended DC Electrical Characteristics
LVCMOS 3.3
LVTTL
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
PCI
SSTL25 Class I
SSTL25 Class II
SSTL18 Class I
SSTL18 Class II
HSTL18 Class I
HSTL18 Class II
1. MachXO2 devices allow LVCMOS inputs to be placed in I/O banks where V
2. MachXO2 devices allow for LVCMOS referenced I/Os which follow applicable JEDEC specifications. For more details about mixed mode
3. The dual function I
4. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
Input/Output
specification. This is referred to as a ratioed input buffer. In a majority of cases this operation follows or exceeds the applicable JEDEC spec-
ification. The cases where MachXO2 devices do not meet the relevant JEDEC specification are documented in the table below.
operation please refer to please refer to TN1202,
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
Standard
Input Standard
2
C pins SCL and SDA are limited to a V
Min. (V)
LVCMOS 33
LVCMOS 25
LVCMOS 18
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
3
V
IL
V
V
V
V
0.35V
0.35V
0.35V
V
V
REF
REF
0.3V
Max. (V)
REF
REF
REF
REF
0.8
0.7
- 0.125 V
- 0.125 V
- 0.18 V
- 0.18
CCIO
CCIO
CCIO
CCIO
- 0.1
- 0.1
MachXO2 sysIO Usage
V
0.65V
0.65V
0.65V
V
V
REF
REF
0.5V
REF
Min. (V)
REF
REF
REF
2.0
1.7
+0.125
+0.125
+ 0.18
+0.18
CCIO
+0.1
+0.1
CCIO
CCIO
CCIO
IL
min of -0.25V or to -0.3V with a duration of <10ns.
V
IH
V
CCIO
3-8
Max. (V)
1.5
1.5
1.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
(V)
Guide.
CCIO
is different from what is specified in the applicable JEDEC
V
0.1V
OL
DC and Switching Characteristics
0.54
0.40
0.40
0.4
0.2
0.4
0.2
0.4
0.2
0.4
0.2
0.4
0.2
NA
NA
NA
(V)
Max.
CCIO
1, 2
MachXO2 Family Data Sheet
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.9V
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
OH
NA
NA
NA
(V)
CCIO
Min.
V
- 0.62
- 0.40
- 0.40
- 0.4
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
IL
0.685
1.687
1.164
Max. (V)
I
OL
(mA)
0.1
0.1
0.1
0.1
0.1
1.5
NA
NA
NA
12
16
24
12
16
12
Max.
4
8
4
8
4
8
4
8
4
8
8
8
8
4
I
OH
(mA)
-0.1
-0.1
-0.1
-0.1
-0.1
-0.5
-12
-16
-24
-12
-16
-12
NA
NA
NA
-4
-8
-4
-8
-4
-8
-4
-8
-2
-6
Max.
8
8
8
4