LCMXO2-4000ZE-1FG484C Lattice, LCMXO2-4000ZE-1FG484C Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LCMXO2-4000ZE-1FG484C
Manufacturer Part Number
LCMXO2-4000ZE-1FG484C
Description
FPGA - Field Programmable Gate Array 4320 LUTs 279 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000ZE-1FG484C
Rohs
yes
Number Of Gates
4 K
Embedded Block Ram - Ebr
92 Kbit
Number Of I/os
279
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 1.26 V, 1.14 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
fpBGA-484
Distributed Ram
34 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
124 uA
Factory Pack Quantity
60
User Flash Memory - Ufm
96 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000ZE-1FG484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks
for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals,
MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such
as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the
global clock network for internally-generated global clocks and control signals.
The maximum frequency for the primary clock network is shown in the MachXO2 External Switching Characteris-
tics table.
The primary clock signals for the MachXO2-256 and MachXO2-640 are generated from eight 17:1 muxes The
available clock sources include eight I/O sources and 9 routing inputs. Primary clock signals for the MachXO2-
640U, MachXO2-1200/U and larger devices are generated from eight 27:1 muxes The available clock sources
include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs.
Figure 2-5. Primary Clocks for MachXO2 Devices
Up to 8
Primary clocks for MachXO2-640U, MachXO2-1200/U and larger devices.
Note: MachXO2-640 and smaller devices do not have inputs from the Edge Clock Divider or PLL
and fewer routing inputs. These devices have 17:1 muxes instead of 27:1 muxes.
8
11
8
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
27:1
2-6
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Dynamic
Enable
Enable
Enable
Enable
Enable
Enable
Clock
Clock
Clock
Clock
Clock
Clock
Switch
Switch
Clock
Clock
Dynamic
Dynamic
Enable
Enable
Clock
Clock
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
Primary Clock 4
Primary Clock 5
MachXO2 Family Data Sheet
Primary Clock 6
Architecture