LCMXO2-4000ZE-1FG484C Lattice, LCMXO2-4000ZE-1FG484C Datasheet - Page 22
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LCMXO2-4000ZE-1FG484C
Manufacturer Part Number
LCMXO2-4000ZE-1FG484C
Description
FPGA - Field Programmable Gate Array 4320 LUTs 279 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-4000ZE-1FG484C
Rohs
yes
Number Of Gates
4 K
Embedded Block Ram - Ebr
92 Kbit
Number Of I/os
279
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 1.26 V, 1.14 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
fpBGA-484
Distributed Ram
34 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
124 uA
Factory Pack Quantity
60
User Flash Memory - Ufm
96 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000ZE-1FG484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Figure 2-15. MachXO2 Output Register Block Diagram (PIO on the Right Edges)
Tri-state Register Block
The tri-state register block registers tri-state control signals from the core of the device before they are passed to
the sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that
then feeds the output.
The tri-state register blocks on the right edge contain an additional register for DDR memory operation. In DDR
memory mode, the register TS input is fed into another register that is clocked using the DQSW90 signal. The out-
put of this register is used as a tri-state control.
Input Gearbox
Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed
as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2-9 shows the
gearbox signals.
Table 2-9. Input Gearbox Signal List
D
ALIGNWD
SCLK
ECLK[1:0]
RST
Q[7:0]
DQSW90
SCLK
D0
D1
TD
Name
D Q
I/O Type
Output
Input
Input
Input
Input
Input
D Q
D/L Q
D/L Q
Q1
Q0
2-18
High-speed data input after programmable delay in PIO A
input register block
Data alignment signal from device core
Slow-speed system clock
High-speed edge clock
Reset
Low-speed data to device core:
Video RX(1:7): Q[6:0]
GDDRX4(1:8): Q[7:0]
GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7
GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3
T0
D Q
MachXO2 Family Data Sheet
Description
Output Register Block
Tristate Register Block
Q
Architecture
TQ