LCMXO2-4000ZE-1BG332C Lattice, LCMXO2-4000ZE-1BG332C Datasheet - Page 27
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LCMXO2-4000ZE-1BG332C
Manufacturer Part Number
LCMXO2-4000ZE-1BG332C
Description
FPGA - Field Programmable Gate Array 4320 LUTs 275 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2280E-4BN256C.pdf
(30 pages)
Specifications of LCMXO2-4000ZE-1BG332C
Rohs
yes
Number Of Gates
4 K
Embedded Block Ram - Ebr
92 Kbit
Number Of I/os
275
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 1.26 V, 1.14 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
caBGA-332
Distributed Ram
34 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
124 uA
Factory Pack Quantity
119
User Flash Memory - Ufm
96 Kbit
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO2-4000ZE-1BG332C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
5.0 MachXO2 Process Reliability Wafer Level Review
Several key fabrication process related parameters have been identified by the foundry that would affect the
Reliability of the End-Product. These parameters are tested during the Development Phase of the Technology.
Passing data (a 10yr lifetime at the reliability junction temperature) must be obtained for three lots minimum for
each parameter before release to production. Normal operating conditions are defined in the Electrical Design
Rules (EDR). These parameters are:
Hot Carrier Immunity (HCI): Effect is a reduction in transistor Idsat. Worst case is low temperature.
Time Dependent Dielectric Breakdown (TDDB): Transistor and capacitor oxide shorts or leakage.
Negative Bias Temperature Instability (NBTI): Symptom is a shift in Vth (also a reduction in Idsat).
Electromigration Lifetime (EML): Symptom is opens within, or shorts between, metal conductors.
Stress Migration (SM): Symptom is a void (open) in a metal Via due to microvoid coalescence.
Table 5.1 – Wafer Level Reliability (WLR) Results
HCI
TDDB
NBTI
EML
SM
Note: Reliability life times are based on listed temperature and use conditions. A Detailed WLR report is available upon request. Lattice
Semiconductor Corporation document #73-106883.
Max Area
0.1% TTF
0.1% TTF
delta Vth
Vgstress
delta Ids
Celsius
Celsius
Celsius
Celsius
Celsius
delta R
delta R
Device
Device
Device
Device
Device
Jmax
TTF
TTF
TTF
Vds
Vg
Vg
3 lots>34yr DC
3 lots>2.5e5 yr 3 lots>1.4e3 yr
3 lots>5.8e5 yr 3 lots>4.2e3 yr
3 lots>2400 yr
3 lots>380 yr
Intermediate
Intermediate
6.65E+05
2.2 cm^2
+100%
-10%
50mv
-1.26
Vd/2
LVN
1.26
LVN
1.26
+5%
LVP
100
100
100
100
25
3 lots>328 yr
Semi-Global
Semi-Global
3 lots>77 yr
3 lots>71yr
6.65E+05
22 cm^2
+100%
100mv
-3.465
-10%
-1.26
-1.26
MVP
+5%
LVP
LVP
100
100
100
100
Vd
25
3 lots>20yr AC 3 lots>684yr
3 lots>1.1e4 yr
3 lots>22 yr
3 lots>25yr
6.65E+05
1 cm^2
+100%
Global
Global
3.465
3.465
-10%
MVN
MVN
Vd/2
+5%
100
100
100
25
27
3 lots>390 yr 3 lots>1.2e3 yr 3 lots>20 yr 3 lots>229yr 3 lots>6690yr
3 lots>70yr
2.85E+05
2.5 cm^2
Top Al
-3.465
-3.465
-10%
MVP
MVP
+5%
100
100
Vd
25
>3.5e6 s DC*
5e-4 cm^2
Lattice Semiconductor Corporation Doc. #25-106923 Rev. F
3 lots
-10%
HVN
HVN
Vd/2
5.25
5.25
100
25
INDEX Return
>1e9 s DC*
5e-4 cm^2 L/S=100nm
-10%
-5.25
3 lots
-5.25
HVP
HVP
100
Vd
25
Intermed.
3.465
IMD
100
Semi-Global
L/S=200nm
3.465
IMD
100