PCA9561D-T NXP Semiconductors, PCA9561D-T Datasheet - Page 7

• Manufacturer Part Number: PCA9561D-T
• Description: EEPROM QUAD 6-BT MULTIPLEX I2C EEPROM
• Manufacturer: NXP Semiconductors

Specifications of PCA9561D-T

• Product Category: EEPROM
• Rohs: yes
• Mounting Style: SMD/SMT
• Package / Case: SOT-163
• Factory Pack Quantity: 2000
• Part # Aliases: PCA9561D,118

NXP Semiconductors
Table 8.
Table 9.
Table 10.
PCA9561
Product data sheet
Write
Read
Default
Write
Read
Default
Read
EEPROM byte 2 register
EEPROM byte 3 register
MUX_IN register
D7
D7
D7
X
X
0
0
0
0
0
6.4 External control signals
If the command register is a command byte, any additional data bytes sent after the
command register will not be acknowledged. If the read/write bit in the address is a
logic 1, then a read operation follows and the data sent out depends on the previously
stored step.
After a valid I
I
its address.
Remark: To ensure data integrity, the non-volatile register must be internally
write-protected when V
dropped below normal operating levels.
The Write Protect (WP) input is used to control the ability to write the content of the
non-volatile registers. If the WP signal is logic 0, the I
contents of the non-volatile registers. If the WP signal is logic 1, data will not be allowed to
be written into the non-volatile registers. In this case, the slave address and the command
code will be acknowledged, but the following data bytes will not be acknowledged and the
EEPROM is not updated.
The factory defaults for the contents of the non-volatile register are all logic 0. These
stored values can be read or written using the I
“Characteristics of the I
The WP, MUX_IN_X, and MUX_SELECT signals have internal pull-up resistors. See
Table 15 “Static characteristics”
signal spike suppression figures.
2
C-bus for 3.6 ms. If the part is addressed prior to this time, the part will not acknowledge
D6
D6
D6
X
X
0
0
0
0
0
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
2
MUX_IN
C-bus write operation to the EEPROM, the part cannot be addressed via the
data F
data F
data F
data F
data F
All information provided in this document is subject to legal disclaimers.
D5
D5
D5
0
0
Rev. 4 — 6 November 2012
DD
2
C-bus”).
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
to the I
MUX_IN
data E
data E
data E
data E
data E
D4
D4
D4
0
0
and
2
Quad 6-bit multiplexed I
C-bus is powered down or V
Table 16 “Dynamic characteristics”
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
data D
data D
data D
data D
data D
D3
D3
D3
0
0
2
C-bus (described in
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
2
data C
data C
data C
data C
data C
C-bus will be able to write the
D2
D2
D2
0
0
2
C-bus EEPROM DIP switch
DD
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
to the component is
MUX_IN
data B
data B
data B
data B
data B
Section 7
D1
D1
D1
0
0
PCA9561
© NXP B.V. 2012. All rights reserved.
for hysteresis and
EEPROM 2
EEPROM 2
EEPROM 3
EEPROM 3
MUX_IN
data A
data A
data A
data A
data A
D0
D0
D0
0
0
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