PCA9561D-T NXP Semiconductors, PCA9561D-T Datasheet

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PCA9561D-T

Manufacturer Part Number
PCA9561D-T
Description
EEPROM QUAD 6-BT MULTIPLEX I2C EEPROM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9561D-T

Product Category
EEPROM
Rohs
yes
Mounting Style
SMD/SMT
Package / Case
SOT-163
Factory Pack Quantity
2000
Part # Aliases
PCA9561D,118
1. General description
2. Features and benefits
The PCA9561 is a 20-pin CMOS device consisting of four 6-bit non-volatile EEPROM
registers, six hardware pin inputs and a 6-bit multiplexed output. It is used for DIP
switch-free or jumper-less system configuration and supports Mobile and Desktop VID
Configuration, where five preset values (four sets of internal non-volatile registers and
one set of external hardware pins) set processor voltage for operation in various
performance or battery conservation sleep modes. The PCA9561 is also useful in server
and telecommunications/networking applications when used to replace DIP switches or
jumpers, since the settings can be easily changed via I
power down the equipment to open the cabinet. The non-volatile memory retains the most
current setting selected before the power is turned off.
The PCA9561 typically resides between the CPU and Voltage Regulator Module (VRM)
when used for CPU VID (Voltage IDentification code) configuration. It is used to bypass
the CPU-defined VID values and provide a different set of VID values to the VRM, if an
increase in the CPU voltage is desired. An increase in CPU voltage combined with an
increase in CPU frequency leads to a performance boost of up to 7.5 %. Lower CPU
voltage reduces power consumption. The main advantage of the PCA9561 over older
devices, such as the PCA9559 or PCA9560, is that it contains four internal non-volatile
EEPROM registers instead of just one or two, allowing five independent settings which
allows a more accurate CPU voltage tuning depending on specific applications.
The PCA9561 has two address pins, allowing up to four devices to be placed on the same
I
2
C-bus or SMBus.
PCA9561
Quad 6-bit multiplexed I
Rev. 4 — 6 November 2012
Selection of non-volatile register_n as source to MUX_OUT pins via I
I
6-bit 5-to-1 multiplexer DIP switch
Four internal non-volatile registers
Internal non-volatile registers programmable and readable via I
Six open-drain multiplexed outputs
400 kHz maximum clock frequency
Operating supply voltage 3.0 V to 3.6 V
5 V and 2.5 V tolerant inputs/outputs
Useful for Speed Step configuration of laptop computer
Two address pins, allowing up to four devices on the I
MUX_IN values readable via I
2
C-bus can override MUX_SELECT pin in selecting output source
2
C-bus
2
C-bus EEPROM DIP switch
2
C-bus/SMBus without having to
2
C-bus
2
Product data sheet
C-bus
2
C-bus

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PCA9561D-T Summary of contents

Page 1

... Quad 6-bit multiplexed I Rev. 4 — 6 November 2012 1. General description The PCA9561 is a 20-pin CMOS device consisting of four 6-bit non-volatile EEPROM registers, six hardware pin inputs and a 6-bit multiplexed output used for DIP switch-free or jumper-less system configuration and supports Mobile and Desktop VID ...

Page 2

... NXP Semiconductors  ESD protection exceeds 200 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA 3. Ordering information Table 1. Ordering information    +85 C. amb Type number Topside ...

Page 3

... NXP Semiconductors 4. Block diagram write protect SCL INPUT FILTER SDA POWER- RESET V SS MUX_SELECT MUX_IN_A MUX_IN_B MUX_IN_C MUX_IN_D MUX_IN_E MUX_IN_F Fig 1. Block diagram of PCA9561 PCA9561 Product data sheet Quad 6-bit multiplexed I NON-VOLATILE 6 REGISTER 0 00 6-BIT EEPROM NON-VOLATILE 6 REGISTER 1 01 ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 3. Symbol SCL SDA A0 MUX_IN_A MUX_IN_B MUX_IN_C MUX_IN_D MUX_IN_E MUX_IN_F V SS MUX_SELECT MUX_OUT_F MUX_OUT_E MUX_OUT_D MUX_OUT_C MUX_OUT_B MUX_OUT_A PCA9561 Product data sheet Quad 6-bit multiplexed I SCL 1 SDA MUX_IN_A 4 MUX_IN_B 5 PCA9561PW ...

Page 5

... NXP Semiconductors 6. Functional description Refer to 6.1 Device address Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9561 is shown in internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. ...

Page 6

... NXP Semiconductors Table 5. Commands register All other combinations are reserved. Command value 6.3 Register description If the Control register byte is an EEPROM address, the next byte will be programmed into that EEPROM address on the following STOP condition logic 0 ...

Page 7

... NXP Semiconductors Table 8. EEPROM byte 2 register D7 D6 Write X X Read 0 0 Default 0 0 Table 9. EEPROM byte 3 register D7 D6 Write X X Read 0 0 Default 0 0 Table 10. MUX_IN register D7 D6 Read the command register is a command byte, any additional data bytes sent after the command register will not be acknowledged ...

Page 8

... NXP Semiconductors Table 11. This table is valid when not overridden by I Input 6.5 Power-on reset When power is applied reset state until V the PCA9561 volatile registers and state machine will initialize to their default states. The MUX_OUT_X pin values depend on the MUX_SELECT logic level: • ...

Page 9

... NXP Semiconductors 7. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...

Page 10

... NXP Semiconductors 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 7 ...

Page 11

... NXP Semiconductors 7.4 Bus transactions Data is transmitted to the PCA9561 registers using the Write Byte transfers (see and Figure Figure 11). slave address SDA START condition Fig 9. Write on one EEPROM, assuming slave address SDA START condition Fig 10 ...

Page 12

... NXP Semiconductors 8. Limiting values Table 12. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol stg [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150  ...

Page 13

... NXP Semiconductors 11. Static characteristics Table 15. Static characteristics Symbol Parameter Supply V supply voltage DD I supply current DD V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I HIGH-level input leakage current LIH ...

Page 14

... NXP Semiconductors 12. Dynamic characteristics Table 16. Dynamic characteristics Symbol Parameter MUX_IN_X  MUX_OUT_X t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay PHL MUX_SELECT  MUX_OUT_X t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay PHL t rise time r t fall time f C load capacitance ...

Page 15

... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 12. Definition of timing Fig 13. Open-drain output enable and disable times 13. Non-volatile storage specifications Table 18. Parameter memory cell data retention number of memory cell write cycles Application note AN250, “I2C DIP Switch” provides additional information on memory cell data retention and the minimum number of write cycles ...

Page 16

... NXP Semiconductors 14. Test information Fig 14. Test circuit for open-drain outputs PCA9561 Product data sheet Quad 6-bit multiplexed I PULSE GENERATOR R = load resistor; 1 k load capacitance; includes jig and probe capacitance termination resistance; should be equal All information provided in this document is subject to legal disclaimers. ...

Page 17

... NXP Semiconductors 15. Package outline TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 18

... NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 19

... NXP Semiconductors 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 20

... NXP Semiconductors Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9561 Product data sheet Quad 6-bit multiplexed I maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...

Page 21

... NXP Semiconductors 17. Soldering: PCB footprints Footprint information for reflow soldering of TSSOP20 package solder land occupied area DIMENSIONS 0.650 0.750 7.200 4.500 1.350 Fig 17. PCB footprint for SOT360-1 (TSSOP20); reflow soldering PCA9561 Product data sheet Quad 6-bit multiplexed I ...

Page 22

... NXP Semiconductors 18. Abbreviations Table 21. Acronym CDM CMOS CPU DIP EEPROM ESD HBM 2 I C-bus PCB SMBus VID VRM PCA9561 Product data sheet Quad 6-bit multiplexed I Abbreviations Description Charged-Device Model Complementary Metal-Oxide Semiconductor Central Processing Unit Dual In-line Package Electrically Erasable Programmable Read-Only Memory ...

Page 23

... Quad 6-bit multiplexed I Data sheet status Product data sheet benefits”, 13th bullet item: deleted phrase “200 V MM per JESD22-A115” information”: deleted PCA9561D (SO20) package option Section 3.1 “Ordering options” description”, modified title changed from “Register Addresses” to “Address register” ...

Page 24

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 25

... PCA9561 Product data sheet Quad 6-bit multiplexed I own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ...

Page 26

... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.1 Control register definition . . . . . . . . . . . . . . . . . 5 6.3 Register description . . . . . . . . . . . . . . . . . . . . . 6 6.4 External control signals . . . . . . . . . . . . . . . . . . 7 6.5 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics of the I 7 ...

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