M95040-RMC6TG STMicroelectronics, M95040-RMC6TG Datasheet - Page 23

• Manufacturer Part Number: M95040-RMC6TG
• Description: EEPROM 4 Kbit SPI BUS EE 10MHz CR 5ms
• Manufacturer: STMicroelectronics

Specifications of M95040-RMC6TG

• Product Category: EEPROM
• Rohs: yes

M950x0 M950x0-W M950x0-R
6.6
Note:
Write to Memory Array (WRITE)
As shown in
Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least
one data byte are then shifted in, on Serial Data input (D). The instruction is terminated by
driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle,
triggered by the rising edge of Chip Select (S), continues for a period t
Table 13: DC characteristics (M950x0, device grade 3)
(M950x0-R, device grade
In the case of
the eighth bit of the data byte has been latched in, indicating that the instruction is being
used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown
in
more than a single byte, starting from the given address towards the end of the same page,
can be written in a single internal Write cycle. If Chip Select (S) still continues to be driven
low, the next byte of input data is shifted in, and used to overwrite the byte at the start of the
current page.
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
The self-timed write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in
S
C
D
Q
Figure 13: Page Write (WRITE)
are Don’t Care.
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and
before the next rising edge of Serial Clock (C) occurs anywhere on the bus)
if Write Protect (W) is low or if the addressed page is in the area protected by the Block
Protect (BP1 and BP0) bits
Figure 12: Byte Write (WRITE)
0
Figure 12: Byte Write (WRITE)
1
High Impedance
2
Instruction
3
A8
4
6)). After this time, the Write in Progress (WIP) bit is reset to 0.
W
5
is internally executed as a sequence of two consecutive
Doc ID 6512 Rev 10
6
7
sequence, the next byte of input data is shifted in, so that
A7
8
A6 A5 A4 A3 A2 A1 A0
9 10 11 12 13 14 15 16 17 18 19
Table 6: Address range
Byte Address
sequence, to send this instruction to the device,
sequence, Chip Select (S) is driven high after
to
Table 20: AC characteristics
bits, the most significant address bits
7
6
5
Data Byte
4
W
3
20 21 22 23
(as specified in
2
1
Instructions
0
AI01442D
23/44