ADG3300BRUZ Analog Devices Inc, ADG3300BRUZ Datasheet - Page 14

• Manufacturer Part Number: ADG3300BRUZ
• Description: IC XLATOR 8CH 1.2/5.5V 20TSSOP
• Manufacturer: Analog Devices Inc

Specifications of ADG3300BRUZ

• Logic Function: Translator, Bidirectional
• Number Of Bits: 8
• Input Type: Logic
• Output Type: Logic
• Data Rate: 50Mbps
• Number Of Channels: 1
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 6ns
• Voltage - Supply: 1.15 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Supply Voltage: 1.15 V ~ 5.5 V
• No. Of Inputs: 8
• Propagation Delay: 6ns
• Logic Type: Level Translator
• Supply Voltage Range: 1.15V To 5.5V
• Logic Case Style: TSSOP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• High Level Output Current: -20uA
• Low Level Output Current: 20uA
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: TSSOP
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.15/1.65V
• Abs. Propagation Delay Time: 35ns
• Mounting: Surface Mount
• Pin Count: 20
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADG3300
TERMINOLOGY
Table 4.
Symbol
V
V
V
V
R
V
V
V
V
C
I
V
V
C
I
t
t
t
t
D
t
t
t
t
t
D
t
t
V
V
I
I
I
I
LY, HiZ
LEN
CCA
CCY
HiZA
HiZY
EN
P, A-Y
R, A-Y
F, A-Y
SKEW, A-Y
PPSKEW, A-Y
P, Y-A
R, Y-A
F, Y-A
SKEW, Y-A
PPSKEW, Y-A
A,HiZ
IHA
ILA
OHA
OLA
IHY
ILY
OHY
OLY
Y
IHEN
ILEN
EN
CCA
CCY
MAX, A-Y
MAX, Y-A
Description
Logic input high voltage at Pins A1 to A8.
Logic input low voltage at Pins A1 to A8.
Logic output high voltage at Pins A1 to A8.
Logic output low voltage at Pins A1 to A8.
Pull-down resistance measured at Pins A1 to A8 when EN = 0.
Logic input high voltage at Pins Y1 to Y8.
Logic input low voltage at Pins Y1 to Y8.
Logic output high voltage at Pins Y1 to Y8.
Logic output low voltage at Pins Y1 to Y8.
Capacitance measured at Pins Y1 to Y8 (EN = 0).
Leakage current at Pins Y1 to Y8 when EN = 0 (high impedance state at Pins Y1 to Y8).
Logic input high voltage at the EN pin.
Logic input low voltage at the EN pin.
Capacitance measured at EN pin.
Enable (EN) pin leakage curent.
Three-state enable time for Pins Y1 to Y8.
Propagation delay when translating logic levels in the A Y direction.
Rise time when translating logic levels in the A Y direction.
Fall time when translating logic levels in the A Y direction.
Guaranteed data rate when translating logic levels in the A Y direction under the driving and loading conditions
specified in Table 1.
Difference between propagation delays on any two channels when translating logic levels in the A Y direction.
Difference in propagation delay between any one channel and the same channel on a different part (under the
same driving/loading conditions) when translating logic levels in the A Y direction.
Propagation delay when translating logic levels in the Y A direction.
Rise time when translating logic levels in the Y A direction.
Fall time when translating logic levels in the Y A direction.
Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions
specified in Table 1.
Difference between propagation delays on any two channels when translating logic levels in the Y A direction.
Difference in propagation delay between any one channel and the same channel on a different part (under the
same driving/loading conditions) when translating in the Y A direction.
V
V
V
V
V
V
CCA
CCY
CCA
CCY
CCA
CCY
supply voltage.
supply voltage.
supply current.
supply current.
supply current during three-state mode (EN = 0).
supply current during three-state mode (EN = 0).
Rev. 0 | Page 14 of 20