74FCT162511CTPAG8 IDT, 74FCT162511CTPAG8 Datasheet - Page 4

• Manufacturer Part Number: 74FCT162511CTPAG8
• Description: Bus Transceivers
• Manufacturer: IDT

Specifications of 74FCT162511CTPAG8

• Rohs: yes
• Part # Aliases: IDT74FCT162511CTPAG8

FUNCTION TABLE
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA,
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
4. H = HIGH Voltage Level
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
and CLKBA.
provided that CLKAB was HIGH before LEAB went LOW.
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
OEAB
H
L
L
L
L
L
L
LEAB
H
H
X
L
L
L
L
Inputs
CLKAB
(1, 4)
H
↑
↑
X
X
X
L
Ax
H
H
X
L
L
X
X
Outputs
B
B
Bx
H
H
Z
L
L
(2)
(3)
4
FUNCTION TABLE
(PARITY CHECKING)
NOTES:
1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses OEBA = L, OEAB
3. In parity checking mode the parity bits will be transmitted unchanged along with the
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered
5. Conditions shown are for the byte A0–A7 and PA1. The byte A8–A15 and PA2 is similiar.
6. The parity error flag PERB is a combined flag for both bytes A0–A7 and A8–A15. If a parity
FUNCTION TABLE
(PARITY GENERATION)
NOTES:
1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge
4. Conditions shown are for the byte A–A7. The byte A8–A15 is similiar but will output
5. The error flag PERB will remain in a high state during parity generation.
Number of inputs that are high
Number of inputs that are high
= H and errors will be indicated on PERA.
corresponding data regardless of parity errors (PB1 = PA1).
clock.
error occurs on either byte PERB will go low. PERB is an open drain output which must
be externally pulled up to achieve a logic HIGH.
is performing generation. B-to-A will not generate parity.
triggered clock.
the parity on PB2.
A
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
0
1, 3, 5 or 7
1, 3, 5 or 7
1, 3, 5, 7 or 9
1, 3, 5, 7 or 9
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
– A
A0 – A7
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
7
and P
A1 (5)
ODD/EVEN
ODD/EVEN
H
H
L
L
(1, 2, 3, 4)
H
H
L
L
(1, 2, 3, 4, 5)
PERB
PB1
H
H
H
H
L
L
L
L
(6)
(6)