74FCT162511CTPAG8 IDT, 74FCT162511CTPAG8 Datasheet

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74FCT162511CTPAG8

Manufacturer Part Number
74FCT162511CTPAG8
Description
Bus Transceivers
Manufacturer
IDT
Datasheet

Specifications of 74FCT162511CTPAG8

Rohs
yes
Part # Aliases
IDT74FCT162511CTPAG8
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical t
• Low input and output leakage ≤ ≤ ≤ ≤ ≤ 1µA (max)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• Balanced Output Drivers:
• Series current limiting resistors
• Generate/Check, Check/Check modes
• Open drain parity error allows wire-OR
• Available in the following packages:
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
© 2009 Integrated Device Technology, Inc.
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
machine model (C = 200pF, R = 0)
– ±24mA (industrial)
– ±16mA (military)
– Industrial: SSOP, TSSOP
– Military: CERPACK
CC
= 5V ±10%
sk(o)
(Open Drain)
ODD/EVEN
(Output Skew) < 250ps, clocked mode
GEN/CHK
CLKAB
PA1,2
OEBA
A0-15
PERA
LEAB
Parity, data
Byte
Parity
Generator/
Checker
18
FAST CMOS 16-BIT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
Data
16
Parity
2
Latch/
Register
Latch/
Register
1
DESCRIPTION:
using advanced dual metal CMOS technology. This high-speed, low-power
transceiver combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched, or clocked modes. The device has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A direction. Error
checking is done at the byte level with separate parity bits for each byte. Separate
error flags exits for each direction with a single error flag indicating an error for
either byte in the A-to-B direction and a second error flag indicating an error for
either byte in the B-to-A direction. The parity error flags are open drain outputs
which can be tied together and/or tied with flags from other devices to form a single
error flag or interrupt. The parity error flags are enabled by the OExx control
pins allowing the designer to disable the error flag during combinational
transitions.
direction while LEBA, CLKBA, and OEBA control the B-to-A direction. GEN/
CHK is only for the selection of A-to-B operation. The B-to-A direction is always
in checking mode. The ODD/EVEN select is common between the two directions.
Except for the ODD/EVEN control, independent operation can be achieved
between the two directions by using the corresponding control lines.
The FCT162511T 16-bit registered/latched transceiver with parity is built
The control pins LEAB, CLKAB, and OEAB control operation in the A-to-B
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
Byte
Parity
Checking
Parity, Data
Parity, data
18
IDT54/74FCT162511AT/CT
18
SEPTEMBER 2009
(Open Drain)
OEAB
B0-15
PB1,2
PERB
LEBA
CLKBA
DSC-2916/4

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74FCT162511CTPAG8 Summary of contents

Page 1

... A0-15 PA1,2 ODD/EVEN Parity, data OEBA PERA (Open Drain) The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES © 2009 Integrated Device Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY DESCRIPTION: The FCT162511T 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology ...

Page 2

... IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER BLOCK DIAGRAM ODD/EVEN OEAB LEBA CLKBA CLKAB LEAB OEBA GEN/CHK PERA (Open Drain ...

Page 3

... IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER PIN CONFIGURATION OEAB 1 LEAB GND GND 14 PERA ...

Page 4

... IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER (1, 4) FUNCTION TABLE Inputs OEAB LEAB CLKAB ↑ ↑ NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. ...

Page 5

... IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial –40°C to +85° 5.0V ±10%; Military Symbol Parameter V Input HIGH Level IH V Input LOW Level IL I Input HIGH Current (Input pins) IH (5) ...

Page 6

... IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER POWER SUPPLY CHARACTERISTICS Symbol Parameter ΔI Quiescent Power Supply Current CC TTL Inputs HIGH I Dynamic Power Supply CCD (4) Current (6) I Total Power Supply Current C NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. ...

Page 7

... IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE (PROPAGATION DELAYS) Symbol Parameter t Propagation Delay, PAx to PBx PLH Ax, PBx to PAx PHL GEN/CHK LOW t Propagation Delay PLH PBx PHL PLH (3) t Propagation Delay Ax to PERB, PAx to PERB ...

Page 8

... H t LEAB or LEBA Pulse Width HIGH W t CLKAB or CLKBA Pulse Width HIGH or LOW W NOTES: 1. See test circuits and waveforms. 2. This parameter is guaranteed but not tested. 3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the port respective to the indicated direction ...

Page 9

... Pulse Generator for All Pulses: Rate ≤ 1.0MHz MILITARY AND INDUSTRIAL TEMPERATURE RANGES Test Open Drain Disable Low Enable Low All Other Tests of the Pulse Generator. OUT PULSE t W PULSE Pulse Width ENABLE DISABLE t t PZL PLZ 3.5V SWITCH 1.5V CLOSED LOW t t ...

Page 10

... FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER ORDERING INFORMATION XX FCT XXX Temp. Range Family Device Type Datasheet Document History 09/06/09 Pg.6 Updated the ordering information by removing the "IDT" notation and non RoHS part. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XXXX XX X Package Process for SALES: ...

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