W65C02S6TPG-14 Western Design Center (WDC), W65C02S6TPG-14 Datasheet - Page 31

• Manufacturer Part Number: W65C02S6TPG-14
• Description: Microprocessors - MPU 8-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C02S6TPG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10

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9.1
The RTL-Code (Register Transfer Level) in Verilog is a synthesizable model. The behavior of this model
is equivalent to the original W65C02S hardcore. The W65C02 RTL-Code is available as the core model
and the W65C02S standard chip model. The standard chip model includes the soft-core and the buffer
ring in RTL-Code.
The W65C02S core uses the same instruction set as the W65C02S.
The only functional difference between the W65C02S and W65C02S core is the RDY pin. The
W65C02S RDY pin is bi-directional. The W65C02S core RDY function is split into 3 pins, RDY,
WAITN and WAITP. The WAITN output goes low and WAITP goes high when a WAI instruction is
executed.
The ESD and latch-up buffers have been removed.
The output from the core is the buffer N-channel and the P-channel transistor drivers.
The following inputs, if not used, must be pulled to the high state: RDY, IRQB, NMIB, BE and SOB.
The timing of the W65C02S core is the same as the W65C02S.
HARD CORE MODEL
SOFT CORE RTL MODEL
Features of the W65C02S Hard Core Model
W65C02 Synthesizable RTL-Code in Verilog HDL
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