W65C02S6TPG-14 Western Design Center (WDC), W65C02S6TPG-14 Datasheet - Page 17

• Manufacturer Part Number: W65C02S6TPG-14
• Description: Microprocessors - MPU 8-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C02S6TPG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10

4.8
Implied addressing uses a single byte instruction. The operand is implicitly defined by the instruction.
4.9
The Program Counter relative addressing mode, sometimes referred to as Relative Addressing, is used
with the Branch instructions. If the condition being tested is met, the second byte of the instruction is
added to the Program Counter and program control is transferred to this new memory location.
4.10 Stack s
The Stack may use memory from 0100 to 01FF and the effective address of the Stack address mode will
always be within this range. Stack addressing refers to all instructions that push or pull data from the
stack, such as Push, Pull, Jump to Subroutine, Return from Subroutine, Interrupts and Return from
Interrupt.
4.11 Zero Page zp
With Zero Page (zp) addressing the second byte of the instruction is the address of the operand in page
zero.
Implied i
Program Counter Relative r
Byte:
Instruction:
Operand address:
Byte:
Instruction:
New PC value
Byte:
Instruction:
Operand address:
Byte:
Instruction:
Operand address:
2
2
2
2
+
offset
effective address
PCH
zp
1
1
1
1
0
1
OpCode
OpCode
OpCode
OpCode
offset
implied
PCL
zp
S
0
0
0
0
17