W65C02S6TPG-14 Western Design Center (WDC), W65C02S6TPG-14 Datasheet - Page 10

• Manufacturer Part Number: W65C02S6TPG-14
• Description: Microprocessors - MPU 8-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C02S6TPG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10

3.8
Phase 2 In (PHI2) is the system clock input to the microprocessor internal clock. During the low power
Standby Mode, PHI2 can be held in either high or low state to preserve the contents of internal registers
since the microprocessor is a fully static design. The Phase 2 Out (PHI2O) signal is generated from
PHI2. Phase 1 Out (PHI1O) is the inverted PHI2 signal. An external oscillator is recommended for
driving PHI2 and used for the main system clock. All production test timing is based on PHI2. PHI2O
and PHI1O were used in older systems for system timing and internal oscillators when an external crystal
was used.
3.9
The Read/Write (RWB) output signal is used to control data transfer. When in the high state, the
microprocessor is reading data from memory or I/O. When in the low state, the Data Bus contains valid
data to be written from the microprocessor and stored at the addressed memory or I/O location. The RWB
signal is set to the high impedance state when Bus Enable (BE) is low.
3.10 Ready (RDY)
A low input logic level on the Ready (RDY) will halt the microprocessor in its current state. Returning
RDY to the high state allows the microprocessor to continue operation following the next PHI2 negative
transition. This bi-directional signal allows the user to single-cycle the microprocessor on all cycles
including write cycles. A negative transition to the low state prior to the falling edge of PHI2 will halt the
microprocessor with the output address lines reflecting the current address being fetched. This assumes
the processor setup time is met. This condition will remain through a subsequent PHI2 in which the ready
signal is low. This feature allows microprocessor interfacing with low-speed memory as well as direct
memory access (DMA). The WAI instruction pulls RDY low signaling the WAit-for-Interrupt condition, thus
RDY is a bi-directional pin. On the W65C02 hard core there is a WAIT output signal that can be used in
ASIC's thus removing the bi-directional signal and RDY becomes only the input. In such a situation the
WAI instruction will pull WAIT low and must be used external of the core to pull RDY low or the processor
will continue as if the WAI never happened.
a falling edge of PHI2 occurs. This again assumes the processor control setup time is met. The RDY pin
no longer has an active pull up. It is suggested that a pull up resistor be used on this pin when not being
used. The RDY pin can still be wire ORed.
3.11 Reset (RESB)
The Reset (RESB) input is used to initialize the microprocessor and start program execution. The RESB
signal must be held low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY)
has no effect while RESB is being held low. All Registers are initialized by software except the Decimal
and Interrupt disable mode select bits of the Processor Status Register (P) are initialized by hardware.
When a positive edge is detected, there will be a reset sequence lasting seven clock cycles. The
program counter is loaded with the reset vector from locations FFFC (low byte) and FFFD (high byte).
This is the start location for program control. RESB should be held high after reset for normal operation.
Processor Status Register (P)
*=software initialized
Phase 2 In (PHI2), Phase 2 Out (PHI2O) and Phase 1 Out (PHI1O)
Read/Write (RWB)
The microprocessor will be released when RDY is high and
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