MAX1224CTC-T Maxim Integrated, MAX1224CTC-T Datasheet - Page 9
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MAX1224CTC-T
Manufacturer Part Number
MAX1224CTC-T
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet
1.MAX1225CTC.pdf
(18 pages)
Specifications of MAX1224CTC-T
Number Of Channels
1
Architecture
SAR
Conversion Rate
1.5 MSPs
Resolution
12 bit
Input Type
Differential
Snr
No
Interface Type
3-Wire, Microwire, QSPI, Serial, SPI
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 70 C
Package / Case
TQFN EP
Maximum Power Dissipation
1349 mW
Minimum Operating Temperature
0 C
Number Of Converters
1
Voltage Reference
External
Figure 3. Functional Diagram
The MAX1224/MAX1225 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. The
serial interface requires only three digital lines (SCLK,
CNVST, and DOUT) and provides easy interfacing to
microprocessors (µPs) and DSPs. Figure 3 shows the
simplified internal structure for the MAX1224/MAX1225.
The equivalent circuit of Figure 4 shows the input archi-
tecture of the MAX1224/MAX1225, which is composed
of a T/H, a comparator, and a switched-capacitor digi-
tal-to-analog converter (DAC). The T/H enters its track-
ing mode on the 14th SCLK rising edge of the previous
conversion. Upon power-up, the T/H enters its tracking
mode immediately. The positive input capacitor is con-
nected to AIN+. The negative input capacitor is con-
nected to AIN-. The T/H enters its hold mode on the
falling edge of CNVST and the difference between the
sampled positive and negative input voltages is con-
verted. The time required for the T/H to acquire an input
signal is determined by how quickly its input capaci-
tance is charged. If the input signal’s source imped-
ance is high, the acquisition time lengthens. The
acquisition time, t
AIN+
AIN-
REF
True-Differential Analog Input T/H
T/H
MAX1224
MAX1225
ACQ
_______________________________________________________________________________________
, is the minimum time needed for
Detailed Description
12-BIT
ADC
SAR
V
DD
RGND
1.5Msps, Single-Supply, Low-Power,
LOGIC AND
CONTROL
TIMING
OUTPUT
BUFFER
GND
V
L
True-Differential, 12-Bit ADCs
DOUT
CNVST
SCLK
the signal to be acquired. It is calculated by the follow-
ing equation:
where R
the input signal.
Note: t
impedance below 12Ω does not significantly affect the
ADC’s AC performance.
The ADC’s input-tracking circuitry has a 15MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sam-
pling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Internal protection diodes that clamp the analog input
to V
from GND - 0.3V to V
inputs must not exceed V
accurate conversions.
Figure 4. Equivalent Input Circuit
DD
AIN+
AIN+
AIN-
AIN-
ACQ
and GND allow the analog input pins to swing
IN
= 200Ω, and RS is the source impedance of
is never less than 125ns, and any source
t
ACQ
C
C
C
C
IN+
IN+
IN-
IN-
≥ 9 x (RS + R
R
R
R
R
IN+
IN+
IN-
IN-
DD
HOLD/CONVERSION MODE
ACQUISITION MODE
Analog Input Protection
+ 0.3V without damage. Both
DD
V
V
AZ
AZ
or be lower than GND for
IN
) x 16pF
Input Bandwidth
COMP
COMP
CAPACITIVE
CAPACITIVE
CONTROL
CONTROL
DAC
LOGIC
DAC
LOGIC
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