MAX1224CTC-T Maxim Integrated, MAX1224CTC-T Datasheet - Page 4

• Manufacturer Part Number: MAX1224CTC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1224CTC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.5 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: No
• Interface Type: 3-Wire, Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: External

1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
TIMING CHARACTERISTICS
(V
Typical values are at V
Figure 1. Detailed Serial-Interface Timing
4
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: 1.5Msps operation guaranteed for V
Note 8: Digital supply current is measured with the V
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Rise to DOUT Transition
DOUT Remains Valid After SCLK
Rise
CNVST Fall to SCLK Fall
CNVST Pulse Width
Power-Up Time; Full Power-Down
Restart Time; Partial Power-Down
DD
CNVST
DOUT
_______________________________________________________________________________________
SCLK
= +2.7V to +3.6V, V
error have been nulled.
ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
speeds for V
PARAMETER
t
SETUP
L
DD
< 2.7V.
= 3V and T
L
t
CL
= V
t
DHOLD
t
t
CH
DOUT
DD
, V
A
REF
SYMBOL
t
= +25°C.)
t
t
PWR-UP
t
DHOLD
SETUP
t
DOUT
t
CSW
t
RCV
t
= 2.048V, f
CH
CL
L
> 2.7V. See the Typical Operating Characteristics section for recommended sampling
V
V
(Note 7)
V
V
(Note 7)
C
C
V
V
V
L
L
L
L
L
L
L
L
L
SCLK
= 2.7V to V
= 1.8V to V
= 2.7V to V
= 1.8V to V
= 1.8V to V
= 1.8V to V
= 1.8V to V
t
= 30pF, V
= 30pF, V
CSW
IH
level equal to V
= 24.0MHz, 50% duty cycle, T
L
L
DD
DD,
DD
DD,
DD
DD
DD
= 2.7V to V
= 1.8V to V
CONDITIONS
minimum recommended
minimum recommended
Figure 2. Load Circuits for Enable/Disable Times
L
a) HIGH-Z TO V
DOUT
, and the V
AND V
6kΩ
DD
DD
OH
TO HIGH-Z
OH
IL
, V
GND
level equal to GND.
OL
TO V
A
= -40°C to +85°C, unless otherwise noted.
OH
,
C
L
18.7
18.7
MIN
10
20
4
TYP
22.5
22.5
b) HIGH-Z TO V
16
DOUT
2
AND V
OL
6kΩ
MAX
TO HIGH-Z
17
24
OL
V
L
, V
GND
C
OH
L
TO V
Cycles
UNITS
ms
ns
ns
ns
ns
ns
ns
OL
,