MAX1224CTC-T Maxim Integrated, MAX1224CTC-T Datasheet - Page 10

• Manufacturer Part Number: MAX1224CTC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1224CTC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1.5 MSPs
• Resolution: 12 bit
• Input Type: Differential
• Snr: No
• Interface Type: 3-Wire, Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: External

Upon initial power-up, the MAX1224/MAX1225 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a conver-
sion is initiated. SCLK runs the conversion and the data
can then be shifted out serially on DOUT.
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. Figures 1
and 5 show timing diagrams, which outline the serial-
interface operation.
1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Figure 5. Interface-Timing Sequence
Figure 6. SPI Interface—Partial Power-Down Mode
10
CNVST
DOUT
SCLK
CNVST
______________________________________________________________________________________
MODE
DOUT
SCLK
HIGH IMPEDANCE
t
SETUP
Initialization After Power-Up
0
1ST SCLK RISING EDGE
and Starting a Conversion
1
0
2
0
Serial Interface
Timing and Control
ONE 8-BIT TRANSFER
NORMAL
3
D11
4
D11
D10
D10
D9
POWER-MODE SELECTION WINDOW
D9
D8
D8
8
D7
D7
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
A CNVST falling edge initiates a conversion sequence:
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the conver-
sion is determined.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions t
SCLK’s rising edge and remains valid 4ns (t
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 12 data bits and 3 leading zeros, at least 16
rising clock edges are needed to shift out these bits.
For continuous operation, pull CNVST high between the
14th and the 16th SCLK rising edges. If CNVST stays
low after the falling edge of the 16th SCLK cycle, the
DOUT line goes to a high-impedance state on either
CNVST’s rising edge or the next SCLK’s rising edge.
D6
D5
D4
D3
PPD
D2
14
D1
t
ACQUIRE
D0
16
CONTINUOUS-CONVERSION
SELECTION WINDOW
DOUT
after each
DHOLD
)