SIM3L156-C-GQ Silicon Labs, SIM3L156-C-GQ Datasheet - Page 38

• Manufacturer Part Number: SIM3L156-C-GQ
• Description: ARM Microcontrollers - MCU 128KB, DC-DC, 32x4 LCD, AES, QFN64
• Manufacturer: Silicon Labs
• Series: SiM3L1xxr

Specifications of SIM3L156-C-GQ

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SiM3L1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.25 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• Interface Type: I2C, SPI, UART, USART
• Length: 10 mm

SiM3L1xx
4.2. I/O
4.2.1. General Features
The SiM3L1xx ports have the following features:
4.2.2. Crossbar
The SiM3L1xx devices have one crossbar with the following features:
The crossbar has a fixed priority for each I/O function and assigns these functions to the port pins. When a digital
resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port pin is assigned,
the crossbar skips that pin when assigning the next selected resource. Additionally, the crossbar will skip port pins
whose associated bits in the PBSKIPEN registers are set. This provides flexibility when designing a system: pins
involved with sensitive analog measurements can be moved away from digital I/O, and peripherals can be moved
around the chip as needed to ease layout constraints.
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5 V tolerant.
Push-pull or open-drain output modes to the VIO or VIORF voltage level.
Analog or digital modes.
Option for high or low output drive strength.
Port Match allows the device to recognize a change on a port pin value.
Internal pull-up resistors are enabled or disabled on a port-by-port basis.
Two external interrupts with up to 16 inputs each provide monitoring capability for external signals.
Internal Pulse Generator Timer (PB0 only) to generate simple square waves and pulses.
Flexible peripheral assignment to port pins.
Pins can be individually skipped to move peripherals as needed for design or layout considerations.
Rev 0.5