SIM3L156-C-GM Silicon Labs, SIM3L156-C-GM Datasheet - Page 36

• Manufacturer Part Number: SIM3L156-C-GM
• Description: ARM Microcontrollers - MCU 128KB, DC-DC, 32x4 LCD, AES, QFN64
• Manufacturer: Silicon Labs

Specifications of SIM3L156-C-GM

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SiM3L1xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFN-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 23
• Interface Type: I2C, SPI
• Length: 9 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 51
• Number Of Timers: 3
• On-chip Dac: Yes
• Program Memory Type: Flash
• Supply Voltage - Max: 3.8 V
• Supply Voltage - Min: 1.8 V

SiM3L1xx
4.1.5.6. Power Mode Summary
The power modes described above are summarized in Table 4.1. Table 3.2 and Table 3.3 provide more information
on the power consumption and wake up times for each mode.
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Power Mode 1 (PM1)
Power Mode 2 (PM2)
Power Mode 3 (PM3)
Power Mode 4 (PM4)
Power Mode 5 (PM5)
Power Mode 6 (PM6)
Power Mode 8 (PM8)
Normal
Mode
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
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Core operating at full speed
Code executing from flash
Core operating at full speed
Code executing from RAM
Core halted
AHB, APB and all peripherals
operational at full speed
All clocks to core and peripherals
stopped
Faster wake enabled by keeping
LFOSC0 or RTC0TCLK active
Core operating at low speed
Code executing from flash
Core operating at low speed
Code executing from RAM
Core halted
AHB, APB and all peripherals
operational at low speed
Low power sleep
LDO regulators are disabled and all
active circuitry operates directly from
VBAT
The following functions are available:
ACCTR0, RTC0, UART0 running
from RTC0TCLK, LPTIMER0, port
match, and the LCD controller
Register and RAM state retention
Table 4.1. SiM3L1xx Power Modes
Description
Rev 0.5
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

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Full device operation
Full device operation
Higher CPU bandwidth than PM0 (RAM
can operate with zero wait states at any
frequency)
Fast wakeup from any interrupt source
Wake on any wake source or reset
source defined in the PMU
Same capabilities as PM0, operating at
lower speed
Lower clock speed enables lower LDO
output settings to save power
Same capabilities as PM1, operating at
lower speed
Lower clock speed enables lower LDO
output settings to save power
Same capabilities as PM2, operating at
lower speed
Lower clock speed enables lower LDO
output settings to save power
When running from LFOSC0, power is
similar to PM3, but the device wakes
much faster
Lowest power consumption
Wake on any wake source or reset
source defined in the PMU
Notes