S9S12GN32F0VLC Freescale Semiconductor, S9S12GN32F0VLC Datasheet - Page 475

• Manufacturer Part Number: S9S12GN32F0VLC
• Description: 16-bit Microcontrollers - MCU 16-bit32k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN32F0VLC

• Product Category: 16-bit Microcontrollers - MCU
• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2048 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

13.3.2.2
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
ETRIGCH[3:0]
Module Base + 0x0001
ETRIGSEL
SRES[1:0]
SMP_DIS
Reset
Field
6–5
3–0
W
7
4
R
ETRIGSEL
ATD Control Register 1 (ATDCTL1)
0
7
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in
A/D Resolution Select — These bits select the resolution of A/D conversion results. See
coding.
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
as source for the external trigger. The coding is summarized in
1
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
If only AN0 should be converted use MULT=0.
SRES1
0
6
SRES1
Figure 13-4. ATD Control Register 1 (ATDCTL1)
0
0
1
1
MC9S12G Family Reference Manual, Rev.1.23
Table 13-3. ATDCTL1 Field Descriptions
SRES0
Table 13-4. A/D Resolution Coding
1
5
SRES0
0
1
0
1
SMP_DIS
0
4
Table
Description
13-5.
ETRIGCH3
A/D Resolution
10-bit data
Reserved
Reserved
1
8-bit data
3
Table
Analog-to-Digital Converter (ADC10B12CV2)
ETRIGCH2
13-5.
1
2
ETRIGCH1
1
1
Table 13-4
ETRIGCH0
for
1
0
477