S9S12GN32F0VLC Freescale Semiconductor, S9S12GN32F0VLC Datasheet - Page 41

• Manufacturer Part Number: S9S12GN32F0VLC
• Description: 16-bit Microcontrollers - MCU 16-bit32k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN32F0VLC

• Product Category: 16-bit Microcontrollers - MCU
• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2048 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

1.3.1
S12 CPU is a high-speed 16-bit processing unit:
1.3.2
On-chip flash memory on the MC9S12G-Family family features the following:
1.3.3
1.3.4
Freescale Semiconductor
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Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
Includes many single-byte instructions. This allows much more efficient use of ROM space.
Extensive set of indexed addressing capabilities, including:
— Using the stack pointer as an indexing register in all indexed operations
— Using the program counter as an indexing register in all but auto increment/decrement mode
— Accumulator offsets using A, B, or D accumulators
— Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)
Up to 240 Kbyte of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
Up to 4 Kbyte EEPROM
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction
— Erase sector size 4 bytes
— Automated program and erase algorithm
— User margin level setting for reads
Up to 11 Kbytes of general-purpose RAM
Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used
as general-purpose I/O
Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J
and AD on per-pin basis
Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis
and on BKGD pin
Control registers to enable/disable open-drain (wired-or) mode on ports S and M
and double fault detection
and double fault detection
S12 16-Bit Central Processor Unit (CPU)
On-Chip Flash with ECC
On-Chip SRAM
Port Integration Module (PIM)
MC9S12G Family Reference Manual, Rev.1.23
Device Overview MC9S12G-Family
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