ispLSI 3448-70LB432 Lattice, ispLSI 3448-70LB432 Datasheet - Page 9

• Manufacturer Part Number: ispLSI 3448-70LB432
• Description: CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
• Manufacturer: Lattice

Specifications of ispLSI 3448-70LB432

• Product Category: CPLD - Complex Programmable Logic Devices
• Memory Type: EEPROM
• Number Of Macrocells: 256
• Maximum Operating Frequency: 83 MHz
• Delay Time: 18 ns
• Number Of Programmable I/os: 224
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: HBGA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 21
• Supply Current: 470 mA
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

Derivations of
Note: Calculations are based on timing specs for the ispLSI 3448-90L.
GOE0,1
Y0,1,2
ispLSI 3448 Timing Model
Reset
(Input)
TOE
Y3,4
I/O
t
t
t
su
h
co
#53
13.7 ns
2.8 ns
4.1 ns
#52
I/O Reg Bypass
D
RST
Register
Input
#24
=
=
=
=
=
=
=
=
=
=
=
=
#25 - 29
t
I/O Cell
su,
Logic + Reg su - Clock (min)
Clock (max) + Reg co + Output
(
(#24+ #30+ #35) + (#38) - (#24+ #30+ #44)
(2.3 + 3.2 + 5.0) + (1.5) - (2.3 + 3.2 + 3.7)
Clock (max) + Reg h - Logic
(
(#24+ #30+ #44) + (#39) - (#24+ #30+ #35)
(2.3 + 3.2 + 3.7) + (5.4) - (2.3 + 3.2 + 5.0)
(
(#24 + #30 + #44) + (#40) + (#45 + #47)
(2.3 + 3.2 + 3.7) + (0.5) + (1.5 + 2.5)
t
t
t
iobp +
iobp +
iobp +
Q
t
h and
t
t
t
grp +
grp +
grp +
t
co from the Product Term Clock
t
t
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
GRP
#30
GRP
#55
#51
#54
t
gsu) - (
t
t
gh) - (
gco) + (
t
4 PT Bypass
XOR Delays
#42 - 44
iobp +
Control
PTs
Feedback
t
iobp +
#34 - 36
20 PT
t
#33
#53
orp +
t
RE
OE
CK
9
grp +
t
grp +
t
Table 2-0042/3448
ob)
GLB
#31
#32
t
ptck(min))
t
1
20ptxor)
Specifications ispLSI 3448
GLB Reg Bypass
D
RST
GLB Reg
Delay
#38 - 41
#37
Q
0902/3448
ORP Bypass
Delay
ORP
ORP
#46
#45
#47, 48
#49, 50
I/O Cell
(Output)
I/O