M4A5-64/32-55JNC Lattice, M4A5-64/32-55JNC Datasheet - Page 13
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M4A5-64/32-55JNC
Manufacturer Part Number
M4A5-64/32-55JNC
Description
CPLD - Complex Programmable Logic Devices 64 MC 32 IO JTAG ISP 5V 5.5ns
Manufacturer
Lattice
Datasheet
1.M4A5-19296-10VNI.pdf
(62 pages)
Specifications of M4A5-64/32-55JNC
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
182 MHz
Delay Time
5.5 ns
Number Of Programmable I/os
32
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
PLCC-44
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
780
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A5-64/32-55JNC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization.
It can be selected to control reset or preset.
Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization
functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch
matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired.
The input switch matrix can send the signal back to the central switch matrix as feedback.
Note:
1. Transparent latch is unaffected by AR, AP
Product Term
Individual
Reset
Power-Up
a. Reset
Reset
Figure 8. Asynchronous Mode Initialization Configurations
D/L/T
AR
0
0
1
1
AP
Table 9. Asynchronous Reset/Preset Operation
AR
Q
ispMACH 4A Family
17466G-014
AP
0
1
0
1
Product Term
CLK/LE
Individual
X
X
X
X
Preset
1
Power-Up
See Table 8
Preset
Q+
1
0
0
b. Preset
D/L/T
AP
AR
Q
17466G-015
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