M4A5-64/32-55JNC Lattice, M4A5-64/32-55JNC Datasheet - Page 10
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M4A5-64/32-55JNC
Manufacturer Part Number
M4A5-64/32-55JNC
Description
CPLD - Complex Programmable Logic Devices 64 MC 32 IO JTAG ISP 5V 5.5ns
Manufacturer
Lattice
Datasheet
1.M4A5-19296-10VNI.pdf
(62 pages)
Specifications of M4A5-64/32-55JNC
Rohs
yes
Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
182 MHz
Delay Time
5.5 ns
Number Of Programmable I/os
32
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
PLCC-44
Mounting Style
SMD/SMT
Number Of Product Terms Per Macro
20
Factory Pack Quantity
780
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A5-64/32-55JNC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization
control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode
chosen only affects clocking and initialization in the macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will
generally be used, since it provides more product terms in the allocator.
10
From Logic Allocator
From PAL-Block
Clock Generator
Individual Clock
Product Terms
Product Term
Product Term
Initialization
Initialization
From Logic
PAL-Clock
Individual macrocell resources
PAL-Block
Generator
Common PAL-block resource
Individual
Allocator
From
Power-Up
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Block CLK0
Block CLK1
Power-Up
Reset
Reset
ispMACH 4A Family
a. Synchronous mode
b. Asynchronous mode
Figure 5. Macrocell
SWAP
SWAP
D/T/L
D/T/L
AP
AP
AR
AR
Q
Q
To Output and Input
Switch Matrices
To Output and Input
Switch Matrices
17466G-009
17466G-010