M4A5-64/32-55JNC Lattice, M4A5-64/32-55JNC Datasheet - Page 11

• Manufacturer Part Number: M4A5-64/32-55JNC
• Description: CPLD - Complex Programmable Logic Devices 64 MC 32 IO JTAG ISP 5V 5.5ns
• Manufacturer: Lattice

Specifications of M4A5-64/32-55JNC

• Rohs: yes
• Memory Type: EEPROM
• Number Of Macrocells: 64
• Maximum Operating Frequency: 182 MHz
• Delay Time: 5.5 ns
• Number Of Programmable I/os: 32
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Package / Case: PLCC-44
• Mounting Style: SMD/SMT
• Number Of Product Terms Per Macro: 20
• Factory Pack Quantity: 780
• Supply Voltage - Max: 5.25 V
• Supply Voltage - Min: 4.75 V

The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The
primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality
is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs
are HIGH.
e. T-type with programmable T polarity
c. Latch with XOR
a. D-type with XOR
L
T
G
D
AP AR
AP AR
AP AR
Figure 6. Primary Macrocell Configurations
g. Combinatorial with programmable polarity
Q
Q
Q
ispMACH 4A Family
b. D-type with programmable D polarity
d. Latch with programmable D polarity
f. Combinatorial with XOR
D
L
G
AP AR
AP AR
Q
Q
17466G-011
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