SSTU32865ET/G,551 NXP Semiconductors, SSTU32865ET/G,551 Datasheet

IC REG BUFFER 28BIT 160-TFBGA

SSTU32865ET/G,551

Manufacturer Part Number
SSTU32865ET/G,551
Description
IC REG BUFFER 28BIT 160-TFBGA
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTU32865ET/G,551

Logic Type
1:2 Registered Buffer with Parity
Supply Voltage
1.7 V ~ 1.9 V
Number Of Bits
28
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935275433551
SSTU32865ET/G-S
SSTU32865ET/G-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTU32865ET/G,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. General description
2. Features
The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by
four (2R
similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTU32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).
The SSTU32865 is packaged in a 160-ball, 12
fine-pitch ball grid array (TFBGA) package, which—while requiring a minimum
9 mm
conventional card technology.
SSTU32865
1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
applications
Rev. 02 — 28 September 2004
28-bit data register supporting DDR2
Fully compliant to JEDEC standard JESD82-9
Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (i.e. 2
Parity checking function across 22 input data bits
Parity out signal
Controlled output impedance drivers enable optimal signal integrity and speed
Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching)
Supports up to 450 MHz clock frequency of operation
Optimized pinout for high-density DDR2 module design
Chip-selects minimize power consumption by gating data outputs from changing state
Supports Stub Series Terminated Logic SSTL_18 data inputs
Differential clock (CK and CK) inputs
Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs
Single 1.8 V supply operation
Available in 160-ball 9 mm
13 mm of board space—allows for adequate signal routing and escape using
4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is
13 mm, 0.65 mm ball pitch TFBGA package
SSTU32864 or 2
18 grid, 0.65 mm ball pitch, thin profile
Product data sheet
SSTU32866)

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SSTU32865ET/G,551 Summary of contents

Page 1

SSTU32865 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM applications Rev. 02 — 28 September 2004 1. General description The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by four ...

Page 2

Philips Semiconductors 3. Applications High-density (e.g. 2 rank by 4) DDR2 registered DIMMs DDR2 Registered DIMMs (RDIMM) desiring parity checking functionality 4. Ordering information Table 1: Ordering information Type number Solder process SSTU32865ET/G Pb-free (SnAgCu solder ball compound) SSTU32865ET SnPb ...

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Philips Semiconductors 5. Functional diagram VREF PARIN D0 D21 DCS0 CSGATEEN DCS1 DCKE0, 2 DCKE1 DODT0, 2 DODT1 RESET CK CK Fig 1. Functional diagram of SSTU32865 9397 750 13799 Product data sheet 1.8 V DDR registered buffer with parity ...

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Philips Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration for TFBGA160 9397 750 13799 Product data sheet 1.8 V DDR registered buffer with parity SSTU32865ET/G SSTU32865ET ball A1 index area ...

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Philips Semiconductors VREF n.c. PARIN n. D11 D9 F D18 D12 G CSGATEEN D15 H CK DCS0 J CK DCS1 K RESET D14 L ...

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Philips Semiconductors 6.2 Pin description Table 2: Pin description Symbol Pin Ungated inputs DCKE0, DCKE1 U1, U2 DODT0, DODT1 T2, T1 Chip Select gated inputs D0 to D21 M1, B1, B2, C1, C2, D2, D1, E1, E2, F2, M2, F1, ...

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Philips Semiconductors Table 2: Pin description …continued Symbol Pin Clock inputs CK, CK J1, K1 Miscellaneous inputs m.c.l. U3, V2, V3 m.c.h. U5, V5 RESET L1 VREF A1, V1 VDDL D4, E4, E6, F4, G4, H4, K4, K5, N4, N5, ...

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Philips Semiconductors 7. Functional description 7.1 Function table Table 3: Function table (each flip-flop) RESET DCS0 DCS1 ...

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Philips Semiconductors [2] This condition assumes PTYERR is HIGH at the crossing of CK going HIGH and CK going LOW. If PTYERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. CSGATEEN is ...

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Philips Semiconductors 7.3 Functional differences to SSTU32864 The SSTU32865 for its basic register functionality, signal definition and performance is based upon the industry-standard SSTU32864, but provides key operational features which differ (at least in part) from the industry-standard register in ...

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Philips Semiconductors RESET DCSn ACT ( PARIN PTYERR HIGH, LOW, or Don't care (1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for ...

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Philips Semiconductors RESET DCSn PDM Qn PARIN PTYERR Unknown input event Fig 5. RESET being held HIGH 9397 750 13799 Product data sheet PDMSS CK to ...

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Philips Semiconductors RESET DCSn (1) CK ( (1) PARIN PTYERR (1) After RESET is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not floating) ...

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Philips Semiconductors PARIN CLOCK (1) This function holds the error for two cycles. For details, see switches from LOW to HIGH”. Fig 7. Parity logic diagram 9397 750 13799 Product data sheet ...

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Philips Semiconductors 8. Limiting values Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V receiver input voltage I V driver output voltage O I input clamp current IK ...

Page 16

Philips Semiconductors 10. Characteristics Table 8: Characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input current I I static standby current DD static operating current I dynamic ...

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Philips Semiconductors Table 9: Timing requirements Over recommended operating conditions, unless otherwise noted. Symbol Parameter f clock frequency clock t pulse duration, CK, CK HIGH or W LOW t differential inputs active time ACT t differential inputs inactive time INACT ...

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Philips Semiconductors 11. Test information 11.1 Test circuit All input pulses are supplied by generators having the following characteristics: Pulse Repetition Rate (PRR) otherwise specified. The outputs are measured one at a time with one transition per measurement. CK inputs ...

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Philips Semiconductors Fig 11. Voltage waveforms; setup and hold times Fig 12. Voltage waveforms; propagation delay times (clock to output) Fig 13. Voltage waveforms; propagation delay times (reset to output) 9397 750 13799 Product data sheet ...

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Philips Semiconductors 11.2 Output slew rate measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 14. Load circuit, HIGH-to-LOW slew measurement Fig 15. Voltage waveforms, ...

Page 21

Philips Semiconductors 11.3 Error output load circuit and voltage measurement All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z (1) C Fig 18. Load circuit, error output measurements Fig ...

Page 22

Philips Semiconductors Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to 9397 750 13799 Product data sheet timing V ICR inputs t LH output waveform 2 clock inputs Rev. 02 — 28 September 2004 SSTU32865 1.8 V ...

Page 23

Philips Semiconductors 12. Package outline TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 0.8 mm ball A1 index area ...

Page 24

Philips Semiconductors 13. Soldering 13.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages ...

Page 25

Philips Semiconductors – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, ...

Page 26

Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, ...

Page 27

Philips Semiconductors 14. Revision history Table 13: Revision history Document ID Release date SSTU32865_2 20040928 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • Section ...

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Philips Semiconductors 15. Data sheet status [1] Level Data sheet status Product status I Objective data Development II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. ...

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Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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