IS43DR32800A-37CBLI-TR ISSI, IS43DR32800A-37CBLI-TR Datasheet - Page 8

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IS43DR32800A-37CBLI-TR

Manufacturer Part Number
IS43DR32800A-37CBLI-TR
Description
DRAM 256M (8Mx32) 266MHz DDR2 1.8v
Manufacturer
ISSI
Datasheet

Specifications of IS43DR32800A-37CBLI-TR

Product Category
DRAM
Rohs
yes
Factory Pack Quantity
1500
IS43DR32800A, IS43/46DR32801A
Input DC logic level
Input AC logic level
Notes:
1. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
AC Input Test Conditions
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the
AC input test signal waveform
8
Symbol Parameter
VIH (ac) ac input logic HIGH
VIL (ac)
Symbol
VREF
VSWING(MAX) Input signal maximum peak to peak swing
SLEW
Symbol 
VIH(dc)
VIL(dc)
VIL(ac) max for falling edges as shown in the below figure.
negative transitions.
ac input logic LOW
Parameter
dc input logic HIGH
dc input logic LOW
Condition
Input reference voltage
Input signal minimum slew rate
V
Falling Slew =
SWING(MAX)
VSSQ - Vpeak
VREF + 0.250
DTF
V
REF
VREF + 0.125
DDR2-400, DDR2-533
Min.
- V
DTF
Min.
- 0.3
IL(ac)
max
VDDQ + Vpeak
VREF - 0.250
Max.
VREF - 0.125
VDDQ + 0.3
Max.
0.5 x VDDQ
Integrated Silicon Solution, Inc. — www.issi.com
Rising Slew =
Value
DTR
1.0
1.0
Units Notes
V
V
Units
1
1
V
V
Units
V/ns
V
V
V
IH(ac)
Notes
V
V
V
V
V
V
V
min - V
DTR
DDQ
IH(ac)
IH(dc)
REF
IL(dc)
IL(ac)
SS
Notes
1
1
2, 3
max
max
REF
min
min
09/08/2010
Rev.  00E

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