IS43DR32800A-37CBLI-TR ISSI, IS43DR32800A-37CBLI-TR Datasheet - Page 11

• Manufacturer Part Number: IS43DR32800A-37CBLI-TR
• Description: DRAM 256M (8Mx32) 266MHz DDR2 1.8v
• Manufacturer: ISSI

Specifications of IS43DR32800A-37CBLI-TR

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 1500

IS43DR32800A, IS43/46DR32801A
Output Buffer Characteristics
Output AC Test Conditions
Output DC Current Drive
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 Ω for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to
OCD Default Characteristics
Notes:
1. Absolute Specifications (TOPER; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing, voltage, and slew rate are no
2. Impedance measurement condition for output source dc current: VDDQ = 1.7 V; VOUT = 1420 mV; (VOUTVDDQ)/IOH must be less than 23.4
3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage.
4. Slew rate measured from VIL(ac) to VIH(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is
6. This represents the step size when the OCD is near 18 Ω at nominal conditions across all process corners/variations and represents only the
7. DRAM output slew rate specification applies to 400 MT/s and 533 MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS specification.
9. DDR2 SDRAM output slew rate test load is defined in Guideline 3 of the AC Timing specification Table.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00E
09/08/2010
Symbol
VOTR
Symbol
IOH(dc)
IOL(dc)
Description
Output impedance
Output impedance step size
for OCD calibration
Pull-up and pull-down
mismatch
Output slew rate
ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are
derived by shifting the desired driver operating point (see Section 3.3 of JESD8-15A) along a 21 Ω load line to define a convenient driver cur-
rent for measurement.
longer applicable if OCD is changed from default settings.
Ω for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V;
VOUT = 280 mV; VOUT/IOL must be less than 23.4 Ω for values of VOUT between 0 V and 280 mV.
guaranteed by design and characterization.
DRAM uncertainty. A 0 Ω value (no calibration) can only be achieved if the OCD impedance is 18 Ω +/-0.75 Ω under nominal conditions.
Parameter
Output Timing Measurement Reference Level
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
Parameter
Sout
See full strength default
driver characteristics
Min
1.5
0
0
Nom
SSTl_18
- 13.4
13.4
SSTL_18
0.5 x VDDQ
Max
1.5
4
5
Units
mA
mA
Unit
V/ns
Ω
Ω
Ω
Notes
1, 3, 4
2, 3, 4
Notes
1
6
1,2,3
1,4,5,7,8,9
Units
V
Notes
1
11