IS46TR16128A-15HBLA1 ISSI, IS46TR16128A-15HBLA1 Datasheet - Page 67

• Manufacturer Part Number: IS46TR16128A-15HBLA1
• Description: DRAM 2G, 1.5v, 1333MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-15HBLA1

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 65 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
Minimum CKE low width for Self Refresh entry to
Valid Clock Requirement after Self Refresh Entry
command; Exit Precharge Power Down with DLL
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
frozen to commands not requiring a locked DLL
Timing of WRA command to Power Down entry
Timing of WRA command to Power Down entry
Control and Address Input pulse width for each
Exit Reset from CKE HIGH to a valid command
Exit (SRX) or Power-Down Exit (PDX) or Reset
Exit Precharge Power Down with DLL frozen to
Timing of MRS command to Power Down entry
Timing of ACT command to Power Down entry
Timing of REF command to Power Down entry
Exit Self Refresh to commands not requiring a
Timing of WR command to Power Down entry
Timing of WR command to Power Down entry
ODT high time without write command or with
Valid Clock Requirement before Self Refresh
Timing of RD/RDA command to Power Down
Timing of PRE or PREA command to Power
Exit Self Refresh to commands requiring a
Exit Power Down with DLL on to any valid
Normal operation Short calibration time
Power-up and RESET calibration time
Normal operation Full calibration time
(SRE) or Power-Down Entry (PDE)
commands requiring a locked DLL
Power Down Entry to Exit Timing
(BL8OTF, BL8MRS, BC4OTF)
(BL8OTF, BL8MRS, BC4OTF)
Command pass disable delay
CKE minimum pulse width
write command and BC4
Power Down Timings
Self Refresh Timings
Calibration Timing
Reset Timing
ODT Timings
Down entry
Parameter
locked DLL
locked DLL
(BC4MRS)
(BC4MRS)
exit timing
input
entry
Exit
tWRAPDEN
tWRAPDEN
tMRSPDEN
tACTPDEN
tREFPDEN
tWRPDEN
tWRPDEN
tRDPDEN
tPRPDEN
tCPDED
tZQoper
tCKESR
tCKSRE
tCKSRX
Symbol
tXSDLL
tXPDLL
ODTH4
tZQCS
tZQinit
tXPR
tCKE
tIPW
tXS
tXP
tPD
DDR3/DDR3L-1866
tCKEmin.: max(3nCK 5 ns)
Min.
tWRPDENmin.: WL + 4 + (tWR / tCK(avg))
tWRPDENmin.: WL + 2 + (tWR / tCK(avg))
535
512
256
tXPRmin.: max(5nCK, tRFC(min) + 10ns)
64
tXSmin.: max(5nCK, tRFC(min) + 10ns)
tWRAPDENmin.: WL + 2 +WR + 1
tCKESRmin.: tCKE(min) + 1 nCK
tCKSREmin.: max(5 nCK, 10 ns)
tCKSRXmin.: max(5 nCK, 10 ns)
tXPDLLmin.: max(10nCK, 24ns)
tCKEmax.: -
tWRAPDENmin.: WL+4+WR+1
tMRSPDENmin.: tMOD(min)
tXPmin.: max(3nCK, 6ns)
tXSDLLmin.: tDLLK(min)
tRDPDENmin.: RL+4+1
tPDmin.: tCKE(min)
tWRAPDENmax.: -
tWRAPDENmax.: -
tMRSPDENmax.: -
tACTPDENmax.: -
tREFPDENmax.: -
tACTPDENmin.: 1
tREFPDENmin.: 1
tPDmax.: 9*tREFI
tWRPDENmax.: -
tWRPDENmax.: -
tRDPDENmax.: -
tPRPDENmin.: 1
tPRPDENmax.: -
Max.
tCPDEDmax.: -
tCKESRmax.: -
tCKSREmax.: -
tCKSRXmax.: -
tCPDEDmin.: 1
tXSDLLmax.: -
tXPDLLmax.: -
ODTH4min.: 4
ODTH4max.: -
tXPRmax.: -
-
-
-
-
tXSmax.: -
tXPmax.: -
DDR3/DDR3L-1866
Min.
Max.
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ps
67
Notes
28
23