AS1542-BTSU ams, AS1542-BTSU Datasheet - Page 14

• Manufacturer Part Number: AS1542-BTSU
• Description: Analog to Digital Converters - ADC
• Manufacturer: ams

Specifications of AS1542-BTSU

• Rohs: yes
• Number Of Channels: 16/8
• Architecture: SAR
• Conversion Rate: 1 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 71 dB
• Interface Type: QSPI, SPI
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Maximum Power Dissipation: 18.4 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1

AS1542
Data Sheet - D e t a i l e d D e s c r i p t i o n
Control Register
The AS1542 control register is a 13-bit, write-only register. Data is loaded into the register from pin DIN on the falling
edge of the SCLK signal. Data is transferred on pin DIN at the same time as the conversion result is read from the
device. The data transferred on pin DIN corresponds to the AS1542 configuration for the next conversion. This
requires 16 serial clocks for every data transfer.
Only the information provided on the first 13 falling clock edges (after CSN falling edge) is loaded to the control regis-
ter. The control register bits are defined in
Table 5. 12-Bit Control Register Format
Table 6. Control Register Bit Definitions
www.austriamicrosystems.com
WRITE
(MSB)
12
Bit Number
10:7
6, 5
12
11
4
3
2
1
0
SEQ
11
ADDR3
ADDR3:ADDR0
10
WEAK/TRIN
PM1, PM0
SHADOW
Bit Name
CODING
SE/FDN
RANGE
WRITE
SEQ
ADDR2
9
ADDR1
Determines if the subsequent 12 bits will be loaded to the control register.
1 = The subsequent 12 bits will be written to the control register.
0 = The subsequent 12 bits are not loaded to the control register and its
contents are unchanged.
This bit is used in conjunction with the SHADOW bit to control the sequencer
(see Table 10 on page 17)
These four address bits and the bit SE/FDN are loaded at the end of the
present conversion sequence, and select which single analog input or pair of
input channels is to be converted in the next serial transfer. The selected input
channel is decoded as shown in
These bits also may select the final channel in a consecutive sequence as
described in
conversion result are also output on DOUT prior to the 12 bits of data
Serial Interface on page
selected by the multiplexer on the 14th SCLK falling edge.
These two power management bits set the mode of operation of the AS1542
(see Table 9 on page
This bit is used in conjunction with the SEQ bit to control the sequencer
Table 10 on page 17)
This bit selects the state of pin DOUT upon completion of the current serial
transfer.
1 = DOUT will be weakly driven to the channel address specified by bit
ADDR3 of the subsequent conversion.
0 = DOUT will return to tri-state at the end of the serial transfer
Interface on page
This bit selects the analog input range to be used for the subsequent
conversion.
This results in conjunction with bit SE/FDN in 4 possible analog input ranges,
as explained in
This bit selects the type of output coding to be used for the conversion result.
1 = The output coding for the next conversion is straight binary.
0 = The output coding for the next conversion is twos complement.
This bit selects in conjunction with the adress bits ADDR3:ADDR0 the input
channels to be used
1 = 16 single-ended input channels
0 = 8 fully-differential channels
8
Table
ADDR0
6.
7
Table 10 on page
Revision 1.00
Table 7 on page 15
PM1
20).
6
(see Table 8 on page
17).
and access the shadow register
20). The next channel to be converted on will be
PM0
and access the shadow register
5
17. The address bits corresponding to the
Description
Table 8 on page
SHADOW WEAK/
4
15).
TRIN
3
15.
RANGE CODING SE/FDN
(see page
2
(see page
(see Serial
1
18).
(see
18).
(LSB)
14 - 29
(see
0