533BB000491DG Silicon Labs, 533BB000491DG Datasheet

533BB000491DG

Manufacturer Part Number

533BB000491DG

Description

Standard Clock Oscillators DUAL XO 6 PIN 0.3PS RS JTR

Manufacturer

Silicon Labs

Series

Si533r

Datasheet

1.533BB000491DG.pdf (12 pages)

Specifications of 533BB000491DG

Product Category

Standard Clock Oscillators

Rohs

yes

Product

Frequency

491 MHz

Frequency Stability

20 PPm

Supply Voltage

2.97 V to 3.63 V

Termination Style

SMD/SMT

Minimum Operating Temperature

- 40 C

Maximum Operating Temperature

+ 85 C

Output Format

LVDS

Dimensions

5 mm W x 7 mm L

Supply Voltage - Max

3.63 V

Supply Voltage - Min

2.97 V

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Features



Applications



Description

The Si533 dual frequency XO utilizes Silicon Laboratories’ advanced

DSPLL

is available with any-frequency output frequency from 10 to 945 MHz and

select frequencies to 1400 MHz. Unlike a traditional XO, where a different

crystal is required for each output frequency, the Si533 uses one fixed crystal

to provide a wide range of output frequencies. This IC based approach allows

the crystal resonator to provide exceptional frequency stability and reliability.

In addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low jitter clocks in noisy environments

typically found in communication systems. The Si533 IC based XO is factory

configurable for a wide variety of user specifications including frequency,

supply

configurations are factory programmed at time of shipment, thereby

eliminating long lead times associated with custom oscillators.

Functional Block Diagram

Rev. 1.2 5/11

Available with any-frequency output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

2 selectable output frequencies

3rd generation DSPLL

jitter performance

3x better frequency stability than

SAW-based oscillators

Pin 1 output enable (OE)

SONET/SDH

Networking

SD/HD video

U A L

voltage,

circuitry to provide a low jitter clock at high frequencies. The Si533

REQUENCY

Z TO

Frequency

Fixed

output

1.4 G H

with superior

format,

Any-frequency

10–1400 MHz

Synthesis

DSPLL®

Clock

and



R Y S TA L

temperature

Clock and data recovery

FPGA/ASIC clock generation

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

)

CLK–

GND

CLK+

stability.

SCILLATOR

Specific

GND

Ordering Information:

(XO )

Pin Assignments:

LVDS/LVPECL/CML

See page 7.

See page 6.

Si5602

(Top View)

CMOS

Si533

E V I S I O N

CLK–

CLK+

Si533

Related parts for 533BB000491DG

533BB000491DG Summary of contents

Page 1

REQUENCY ( 1 Features  Available with any-frequency output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz  2 selectable output frequencies ®  ...

S i 533 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current Output Enable (OE) 2 and Frequency Select (FS) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering ...

Page 3

Table 2. CLK± Output Frequency Characteristics (Continued) Parameter Symbol Total Stability 4 Powerup Time t OSC Settling Time After FS Change t FRQ Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. 2. Specified at time ...

Page 4

S i 533 Table 4. CLK± Output Phase Jitter Parameter Symbol 1 Phase Jitter (RMS) for F > 500 MHz OUT 1 Phase Jitter (RMS) for F of 125 to 500 MHz OUT Phase Jitter (RMS) for ...

Page 5

Table 7. Absolute Maximum Ratings Parameter Maximum Operating Temperature Supply Voltage, 1.8 V Option Supply Voltage, 2.5/3.3 V Option Input Voltage (any input pin) Storage Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile) Soldering Temperature Time @ T ...

Page 6

S i 533 2. Pin Descriptions GND 3 LVDS/LVPECL/CML Pin # Symbol LVDS/LVPECL/CML Function 1 OE clock output disabled (outputs tristated clock output enabled 2 FS First frequency selected 1 ...

Page 7

Ordering Information The Si533 XO supports a variety of options including frequency, temperature stability, output format, and V Specific device configurations are programmed into the Si533 at time of shipment. Configurations can be specified using the Part Number Configuration ...

Page 8

S i 533 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si533. Table 9 lists the values for the dimensions shown in the illustration. Table 9. Package Diagram Dimensions (mm) Dimension A b ...

Page 9

Si533 Mark Specification Figure 3 illustrates the mark specification for the Si533. Table 10 lists the line information. Table 10. Si53x Top Mark Description Line Position 1 1–10 “SiLabs 533” 2 1–10 Si533: Option1 + Option2 + ConfigNum(6) + ...

Page 10

S i 533 6. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si533. Table 11 lists the values for the dimensions shown in the illustration. Table 11. PCB Land Pattern Dimensions (mm) Dimension D2 ...

Page 11

OCUMENT HANGE IST Revision 1.0 to Revision 1.1  Updated Table 1, “Recommended Operating Conditions,” on page 2. Device maintains stable operation over –40 to +85 ºC  operating temperature range. Supply current specifications updated for revision ...

Page 12

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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