PCA2129T/Q900/2,51 NXP Semiconductors, PCA2129T/Q900/2,51 Datasheet - Page 60

• Manufacturer Part Number: PCA2129T/Q900/2,51
• Description: Real Time Clock
• Manufacturer: NXP Semiconductors
• Series: PCA2129r

Specifications of PCA2129T/Q900/2,51

• Rohs: yes
• Function: Clock, Calendar, Alarm, Watchdog, Timestamp
• Rtc Bus Interface: I2C, SPI
• Date Format: Binary
• Time Format: Binary
• Supply Voltage - Max: 4.2 V
• Supply Voltage - Min: 1.8 V
• Maximum Operating Temperature: + 80 C
• Minimum Operating Temperature: - 30 C
• Mounting Style: SMD/SMT
• Package / Case: SOP-16
• Battery Backup Switching: Yes

NXP Semiconductors
PCA2129T
Product data sheet
13.2 I
Table 56.
All timing characteristics are valid within the operating supply voltage and ambient temperature
range and reference to 30 % and 70 % with an input voltage swing of V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Symbol Parameter
Pin SCL
f
t
t
Pin SDA/CE
t
t
t
t
t
t
t
t
t
t
t
Pins SCL and SDA/CE
2
SCL
LOW
HIGH
SU;DAT
HD;DAT
BUF
SU;STO
HD;STA
SU;STA
r
f
VD;ACK
VD;DAT
SP
C-bus timing characteristics
The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus
interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be
disabled for DC operation.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
C
The maximum t
t
and the SDA/SCL bus lines without exceeding the maximum t
t
t
Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
f
VD;ACK
VD;DAT
b
is 250 ns. This allows series protection resistors to be connected between the SDA/CE pin, the SCL pin,
is the total capacitance of one bus line in pF.
SCL clock frequency
LOW period of the SCL
clock
HIGH period of the SCL
clock
data set-up time
data hold time
bus free time between a
STOP and START
condition
set-up time for STOP
condition
hold time (repeated)
START condition
set-up time for a
repeated START
condition
rise time of both SDA
and SCL signals
fall time of both SDA and
SCL signals
data valid acknowledge
time
data valid time
pulse width of spikes
that must be suppressed
by the input filter
is the minimum time for valid SDA (out) data following SCL LOW.
is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW.
I
2
C-bus characteristics
All information provided in this document is subject to legal disclaimers.
f
for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage,
Rev. 3 — 24 January 2013
Accurate RTC with integrated quartz crystal for automotive
[2][3][4]
[2][3][4]
[1]
[5]
[6]
[7]
250
Standard mode
Min
0
4.7
4.0
0
4.7
4.0
4.0
4.7
-
-
0.1
300
-
Max
100
-
-
-
-
-
-
-
-
1000
300
3.45
-
50
f
.
Fast-mode (Fm)
Min
0
1.3
0.6
100
0
1.3
0.6
0.6
0.6
20 + 0.1C
20 + 0.1C
0.1
75
-
SS
to V
PCA2129T
DD
© NXP B.V. 2013. All rights reserved.
b
b
(see
Max
400
-
-
-
-
-
-
-
-
300
300
0.9
-
50
Figure
60 of 72
43).
Unit
kHz
s
s
ns
ns
s
s
s
s
ns
ns
s
ns
ns
IL
of