PCA2129T/Q900/2,51 NXP Semiconductors, PCA2129T/Q900/2,51 Datasheet - Page 49

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PCA2129T/Q900/2,51

Manufacturer Part Number
PCA2129T/Q900/2,51
Description
Real Time Clock
Manufacturer
NXP Semiconductors
Series
PCA2129r
Datasheet

Specifications of PCA2129T/Q900/2,51

Rohs
yes
Function
Clock, Calendar, Alarm, Watchdog, Timestamp
Rtc Bus Interface
I2C, SPI
Date Format
Binary
Time Format
Binary
Supply Voltage - Max
4.2 V
Supply Voltage - Min
1.8 V
Maximum Operating Temperature
+ 80 C
Minimum Operating Temperature
- 30 C
Mounting Style
SMD/SMT
Package / Case
SOP-16
Battery Backup Switching
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA2129T/Q900/2,51
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
PCA2129T
Product data sheet
Fig 33. System configuration
SCL
SDA
9.2.4 Acknowledge
9.2.5 I
TRANSMITTER
RECEIVER
MASTER
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
Acknowledgement on the I
After a start condition, a valid hardware address has to be sent to a PCA2129T device.
The appropriate I
is shown in
2
Fig 34. Acknowledgement on the I
C-bus protocol
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
by transmitter
data output
by receiver
data output
SCL from
master
Table
RECEIVER
SLAVE
All information provided in this document is subject to legal disclaimers.
2
51.
C-bus slave address is 1010001. The entire I
condition
START
Rev. 3 — 24 January 2013
S
Accurate RTC with integrated quartz crystal for automotive
2
C-bus is illustrated in
TRANSMITTER
RECEIVER
SLAVE
1
2
C-bus
2
TRANSMITTER
Figure
MASTER
34.
not acknowledge
acknowledge
2
8
C-bus slave address byte
TRANSMITTER
PCA2129T
RECEIVER
MASTER
acknowledgement
clock pulse for
© NXP B.V. 2013. All rights reserved.
mba605
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mbc602
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