CSPUA877BVG IDT, CSPUA877BVG Datasheet - Page 6

• Manufacturer Part Number: CSPUA877BVG
• Description: Clock Drivers & Distribution 1.8V PLL Differ 1
• Manufacturer: IDT

Specifications of CSPUA877BVG

• Rohs: yes
• Part # Aliases: IDTCSPUA877BVG

AC ELECTRICAL CHARACTERISTICS
NOTES:
1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage
2. Refers to transition of non-inverting output.
3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other.
4. To eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK, CLK) and feedback clock input (FBIN, FBIN) are recommended
5. Static phase offset does not include jitter.
6. V
7. In the frequency range of 271 - 410MHz, the min and max values for t
IDTCSPUA877
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
t
t
JIT(PER) (3,7)
The PLL on the CSPUA877 will meet all the above test parameters while supporting SSC synthesizers with the following parameters:
CSPUA877 PLL designs should target the value below to minimize SSC-induced skew:
only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50Ω equal length cables with SMA connectors
on the test board.
to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nominal values is not mandatory if it can be adequately demonstrated
that alternative characteristics meet the requirements of the registered DDR2 DIMM application.
of the 160 - 270MHz range. Also, the sum of the specified values for
for
JIT(HPER) (3)
t
Symbol
s
(∅)DYN (7)
Σt
t
t
OX
t
Σt
V
JIT(CC+)
SK(O) (7)
LR(O) (4)
JIT(CC-)
t
s
(∅) (5)
| t
t
(SU) (7)
t
OX (6)
LR(I)
DIS
(H) (7)
EN
is specified at the DDR DRAM clock input or test load.
(∅)DYN
| and t
Description
OE to any Y/Y
OE to any Y/Y
Output Enable (OE)
Input Clock Slew Rate, measured single-ended
Output Clock Slew Rate, measured single-ended 160 to 410
Output Differential-Pair Cross-Voltage
Cycle-to-Cycle Period Jitter
Cycle-to-Cycle Period Jitter
Static Phase Offset
Dynamic Phase Offset
Output Clock Skew
Period Jitter
Half-Period Jitter
| t
| t
SSC Modulation Frequency
SSC Clock Input Frequency Deviation
PLL Loop Bandwidth (-3dB from unity gain)
SK(O)
JIT(PER)
(∅)DYN
must meet the requirement for
| + t
| + | t
SK(O)
(∅)DYN
| + t
SK(O)
Σt
(H).
| t
JIT(PER)
JIT
(
f
160 to 410
160 to 410
160 to 410
160 to 410
160 to 410
160 to 410
160 to 410
160 to 410
160 to 270
271 to 410
160 to 270
271 to 410
160 to 270
271 to 410
160 to 270
271 to 410
271 to 410
271 to 410
PER
CK
) and
(MHz)
|, | t
(1)
t
(∅)DYN
(∅)DYN
6
, and the max value for t
|, and t
SK(O)
must meet the requirement for
SK
(
O
), must not exceed the corresponding min and max values
(V
t
t
(∅)DYN(MIN)
JIT(PER)MIN
COMMERCIAL TEMPERATURE RANGE
DDQ
Min.
0.5
1.5
-50
-50
-40
-75
-50
⎯
⎯
⎯
⎯
⎯
⎯
30
1
0
0
0
2
/2) -0.1
Σt
(SU),
Typ.
2.5
2.5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
and the sum of the specified values
(2)
(V
t
t
(∅)DYN(MAX)
JIT(PER)MAX
DDQ
t
SK(O)MAX
Max.
⎯
-40
0.5
⎯
40
50
50
40
40
75
50
80
60
33
8
8
4
3
/2) +0.1
MHz
V/ns
V/ns
KHz
Unit
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
V