CSPUA877BVG IDT, CSPUA877BVG Datasheet - Page 11

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CSPUA877BVG

Manufacturer Part Number
CSPUA877BVG
Description
Clock Drivers & Distribution 1.8V PLL Differ 1
Manufacturer
IDT
Datasheet

Specifications of CSPUA877BVG

Rohs
yes
Part # Aliases
IDTCSPUA877BVG
TEST CIRCUIT AND SWITCHING WAVEFORMS
APPLICATION INFORMATION
NOTES:
Place all decoupling capacitors as close to the CSPUA877 pins as possible.
Use wide traces for A
Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8Ω DC max., 600Ω at 100MHz).
IDTCSPUA877
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
Clock Structure
GND
V
DDQ
#1
#2
CARD
CARD
VIA
VIA
Clock Inputs and
Outputs, OE
VDD
and AGND.
20%
Recommended Filtering for the Analog and Digital Power Supplies (AV
t
SLR(I/O)
BEAD
80%
0603
# of SDRAM Loads per Clock
4.7uF
1206
=
t
V
R(I),
80%
t
2
4
R(I/O)
t
R(O)
V
20%
Input and Output Slew Rates
0.1uF
0603
11
2200pF
t
0603
Min.
SLF(I/O)
Clock Loading on the PLL outputs (pF)
3
6
t
F(I),
t
F(O)
=
AV
AGND
CSPUA877
DD
V
80%
COMMERCIAL TEMPERATURE RANGE
DD
80%
t
F(I/O)
and V
V
GND
DDQ
V
20%
DDQ
20%
1
)
V
Max.
10
ID
5
10
, V
OD
0.1uF
0603

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