5V9351PFGI IDT, 5V9351PFGI Datasheet - Page 3

• Manufacturer Part Number: 5V9351PFGI
• Description: Clock Drivers & Distribution 4 Bank PLL Clock Dvr w/PECL Input
• Manufacturer: IDT

Specifications of 5V9351PFGI

• Rohs: yes
• Part # Aliases: IDT5V9351PFGI

PIN DESCRIPTION
FUNCTIONALITY
NOTE:
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to FBIN.
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
PECL-CLK
PECL-CLK
REF_SEL
PLL_EN
f
REF_SEL
Q
Q
SEL(D:A)
Name
TCLK
FBIN
PLL_EN
V
GND
Control
FSELA
FSELB
FSELC
FSELD
V
OE
C (1:0)
D (4:0)
Q
Q
CCA
CC
OE
A
B
Terminal
7, 13, 17, 21,
12, 14, 16,
11, 15, 19,
3, 4, 5, 6
22, 24
18, 20
23, 27
25, 29
No.
8, 9
30
32
10
28
26
31
2
1
Default
0
1
0
0
0
0
0
Ground
Type
PWR
PWR
O
O
O
O
I
I
I
I
I
I
I
Selects PECL_CLK as reference clock
Test mode with PLL Disabled
Outputs enabled
Q
Q
Q
Q
A
B
C
D
Description
Differential clock reference, LOW voltage positive ECL input
Single-ended reference clock signal or test clock
Feedback signal input
Reference clock input
Frequency control pin
Output enable/disable
Bank A clock output
Bank B clock output
Bank C clock output
Bank D clock output
Positive power supply for PLL
Positive power supply for I/O and core
Negative power supply
PLL enable input. When set HIGH, PLL is enabled. When set LOW, PLL is disabled.
= V
= V
= V
= V
CO
CO
CO
CO
÷ 2
÷ 4
÷ 4
÷ 4
0
3
Selects TCLK as reference clock
PLL Enabled
Outputs disabled
Q
Q
Q
Q
A
B
C
D
= V
= V
= V
= V
CO
CO
CO
CO
÷ 4
÷ 8
÷ 8
÷ 8
INDUSTRIAL TEMPERATURE RANGE
1