P89LPC936FDH-S Philips, P89LPC936FDH-S Datasheet - Page 37

• Manufacturer Part Number: P89LPC936FDH-S
• Description: ram, tssop, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, mcu, ic
• Manufacturer: Philips

Philips Semiconductors
9397 750 15113
Product data sheet
8.19.7 Alternating output mode
8.19.8 PLL operation
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
The PWM module features a PLL that can be used to generate a CCUCLK frequency
between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic
PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or
higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output
signal of 32 times the input frequency. This signal is used to clock the timer. The user will
have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the
SFR register TCR21. The PLL frequency can be expressed as shown in
Where: N is the value of PLLDV.3 to PLLDV.0.
Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to
PLL frequency
Fig 12. Alternate output mode
=
----------------- -
PCLK
N
+
1
Rev. 06 — 20 June 2005
8-bit microcontroller with accelerated two-clock 80C51 core
P89LPC933/934/935/936
002aaa895
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
0
PWM OUTPUT A (or C) (P2.6)
PWM OUTPUT B (or D) (P1.6)
TIMER VALUE
Equation
1.
PCLK
37 of 75
(1)
16
.