P89LPC936FDH-S Philips, P89LPC936FDH-S Datasheet - Page 23
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P89LPC936FDH-S
Manufacturer Part Number
P89LPC936FDH-S
Description
ram, tssop, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, mcu, ic
Manufacturer
Philips
Datasheet
1.P89LPC936FDH-S.pdf
(75 pages)
- Current page: 23 of 75
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Table 6:
* indicates SFRs that are bit addressable.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Name
TL2
TMOD
TOR2H
TOR2L
TPCR2H
TPCR2L
TRIM
WDCON
WDL
WFEED1
WFEED2
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
All ports are in input only (high-impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset source that affects these SFRs is power-on reset.
Special function registers - P89LPC935/936
Description
CCU timer low
Timer 0 and 1 mode
CCU reload register high
CCU reload register low
Prescaler control register high CBH
Prescaler control register low
Internal oscillator trim register
Watchdog control register
Watchdog load
Watchdog feed 1
Watchdog feed 2
SFR
addr.
CCH
CEH
CAH TPCR2L.
CFH
A7H
C1H
C2H
C3H
89H
96H
Bit functions and addresses
T1GATE
RCCLK
PRE2
MSB
7
-
…continued
TPCR2L.
ENCLK
T1C/T
PRE1
6
-
TPCR2L.
TRIM.5
T1M1
PRE0
5
-
TPCR2L.
TRIM.4
T1M0
4
-
-
TPCR2L.
T0GATE
TRIM.3
3
-
-
TPCR2L.
WDRUN
TRIM.2
T0C/T
2
-
TPCR2H.
TPCR2L.
WDTOF
TRIM.1
T0M1
1
1
TPCR2H.
TPCR2L.
WDCLK
TRIM.0
T0M0
LSB
0
0
Reset value
Hex
00
00
00
00
00
00
FF
[6] [5]
[7] [5]
Binary
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xx00
0000 0000
1111 1111
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