P89LPC936FDH-S Philips, P89LPC936FDH-S Datasheet - Page 17
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P89LPC936FDH-S
Manufacturer Part Number
P89LPC936FDH-S
Description
ram, tssop, flash, Microcontrollers, Microprocessors, Semiconductors and Actives, mcu, ic
Manufacturer
Philips
Datasheet
1.P89LPC936FDH-S.pdf
(75 pages)
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Table 5:
* indicates SFRs that are bit addressable.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Name
WDL
WFEED1
WFEED2
Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise specified, ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset values shown for these bits are logic 0s although they are unknown when read.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
All ports are in input only (high-impedance) state after power-up.
The RSTSRC register reflects the cause of the P89LPC933/934/935/936 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset
value is xx11 0000.
The only reset source that affects these SFRs is power-on reset.
On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
Special function registers - P89LPC933/934
Description
Watchdog load
Watchdog feed 1
Watchdog feed 2
SFR
addr.
C1H
C2H
C3H
Bit functions and addresses
MSB
…continued
LSB
Reset value
Hex
FF
Binary
1111 1111
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