AT45DB021D-SSH-B-RET Atmel, AT45DB021D-SSH-B-RET Datasheet - Page 34

• Manufacturer Part Number: AT45DB021D-SSH-B-RET
• Manufacturer: Atmel

34
Figure 17-5. Atmel RapidS Mode
Figure 17-6. Reset Timing
Note:
Figure 17-7. Command Sequence for Read/Write Operations for Page Size 256-Bytes (Except Status Register
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
The Master is the host controller and the Slave is the DataFlash
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
SI (INPUT)
Slave
SO (OUTPUT)
Atmel AT45DB021D
A.
B.
C.
D.
E.
F.
G. Master clocks in first bit of BYTE-SO
H. Slave clocks out second bit of BYTE-SO
I.
MSB
SI (INPUT)
MOSI
MISO
SCK
Master clocks out first bit of BYTE-MOSI on the rising edge of SCK
Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK
Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK
Last bit of BYTE-MOSI is clocked out from the Master
Last bit of BYTE-MOSI is clocked into the slave
Slave clocks out first bit of BYTE-SO
Master clocks in last bit of BYTE-SO
RESET
CS
The CS signal should be in the high state before the RESET signal is deasserted
SCK
CS
Read, Manufacturer and Device ID Read)
6 Don’t Care
X X X X X X
Bits
A
1
B
MSB
CMD
HIGH IMPEDANCE
C
2
X X
3
Page Address
8 bits
(A17 - A8)
X X X X X X X X
4
BYTE-MOSI
8 bits
5
6
(A7 - A0/BFA7 - BFA0)
8 bits
Byte/Buffer Address
7
D
X X X X X X X X
8
E
LSB
F
1
G
MSB
2
H
3
t RST
t REC
4
LSB
HIGH IMPEDANCE
BYTE-SO
5
6
t CSS
7
3638J–DFLASH–5/10
8
I
LSB
1