AM186CC-50KC\W C AMD, AM186CC-50KC\W C Datasheet - Page 80
![no-image](/images/no-image-200.jpg)
AM186CC-50KC\W C
Manufacturer Part Number
AM186CC-50KC\W C
Description
Manufacturer
AMD
Datasheet
1.AM186CC-50KCW_C.pdf
(112 pages)
- Current page: 80 of 112
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Notes:
1. All timing parameters are measured at V
80
402
403
404
No.
15
20
25
27
30
31
68
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
1
2
5
7
A17, A15, A13, A11,
A9, A7, A5, A3, A1
Symbol
t
t
t
t
t
CHRAS
CHCAS
t
t
t
CVCTV
t
CLDOX
CVCTX
t
t
t
t
t
DVCL
CLDX
CLDV
CLRH
CHAV
COLV
CLAV
CLAZ
CLRL
RAS0, RAS1
CAS0, CAS1
AD15–A0
CLKOUT
Data in setup
Data in hold
AD address valid delay
Data valid delay
AD address float delay
Control active delay 1
RD active delay
RD inactive delay
Data hold time
Control inactive delay
CLKOUT High to A address valid
Column address valid delay
Change in RAS delay
Change in CAS delay
RD
Parameter
Figure 38. DRAM Read Cycle without Wait-States Waveform
Description
Am186™CC Communications Controller Data Sheet
T4
CC
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
68
Table 26. DRAM Timing
5
Row
T1
Min
10
3
0
0
0
0
0
0
0
0
0
0
3
3
403
25 MHz
Addr.
Max
20
20
20
20
20
20
20
20
20
20
20
—
—
—
25
15
T2
402
1
Min
5
2
0
0
0
0
0
0
0
0
0
3
3
0
40 MHz
Preliminary
404
Max
12
12
12
12
12
12
12
12
12
12
12
Column
—
—
—
T3
(Commercial Only)
1
Data
Min
5
2
0
0
0
0
0
0
0
0
0
0
3
3
50 MHz
403
27
2
T4
Max
10
10
10
10
10
10
10
10
10
10
10
—
—
—
404
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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