AM186CC-50KC\W C AMD, AM186CC-50KC\W C Datasheet - Page 72

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AM186CC-50KC\W C

Manufacturer Part Number
AM186CC-50KC\W C
Description
Manufacturer
AMD
Datasheet
Notes:
1. All timing parameters are measured at V
72
CLKIN Requirements for 4x PLL Mode
CLKIN Requirements for 2x PLL Mode
No.
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
1
2
3
4
5
1
2
3
4
5
Symbol
t
t
t
t
t
t
t
t
CLKOUT
t
t
UCHCK
UCHCK
UCLCK
UCKHL
UCKLH
UCLCK
UCKHL
UCKLH
UCKIN
UCKIN
USBX2
USBX1
X2
X1
Figure 28. System Clock Timing Waveforms—Active Mode (PLL 1x Mode)
Description
USBX1 period
USBX1 Low time (1.5 V)
USBX1 High time (1.5 V)
USBX1 fall time (3.5 to 1.0 V)
USBX1 rise time (1.0 to 3.5 V)
USBX1 period
USBX1 Low time (1.5 V)
USBX1 High time (1.5 V)
USBX1 fall time (3.5 to 1.0 V)
USBX1 rise time (1.0 to 3.5 V)
40
Am186™CC Communications Controller Data Sheet
4
Figure 29. USB Clock Timing Waveforms
Parameter
69
CC
Table 19. USB Clocks Timing
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
39
1
36
5
42
2
37
38
3
1
46
44
43
Min
80
35
35
40
15
15
Preliminary
48 MHz
45
Max
85
42
5
5
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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