AM186CC-50KC\W C AMD, AM186CC-50KC\W C Datasheet - Page 33

• Manufacturer Part Number: AM186CC-50KC\W C
• Manufacturer: AMD

Timer 2 is not connected to any external pins. It can be
used by software to generate interrupts, or it can be
polled for real-time coding and time-delay applications.
Timer 2 can also be used as a prescaler to Timer 0 and
Timer 1, or as a DMA request source.
The source clock for Timer 2 is one-fourth of the
system clock frequency. The source clock for Timers 0
and 1 can be configured to be one-fourth of the system
clock, or they can be driven from their respective timer
input pins. When driven from a timer input pin, the timer
is counting the “event” of an input transition.
The Am186CC microcontroller also provides a pulse width
demodulation (PWD) option so that a toggling input signal’s
Low state and High state durations can be measured.
Hardware Watchdog Timer
The Am186CC microcontroller provides a full-featured
watchdog timer, which includes the ability to generate
Non-Maskable Interrupts (NMIs), microcontroller
resets, and system resets when the timeout value is
reached. The timeout value is programmable and
ranges from 2
The watchdog timer is used to regain control when a
system has failed due to a software error or to failure of
an external device to respond in the expected way.
Software errors can sometimes be resolved by
recapturing control of the execution sequence via a
watchdog-timer-generated NMI. When an external
device fails to respond, or responds incorrectly, it may
be necessary to reset the controller or the entire
system, including external devices. The Am186CC
watchdog timer provides the flexibility to support both
NMI and reset generation.
Memory and Peripheral Interface
System Interfaces
The Am186CC bus interface controls all accesses to
the peripheral control block (PCB), memory-mapped
and I/O-mapped external peripherals, and memory
devices. Internal peripherals are accessed by the bus
interface through the PCB.
The Am186CC bus interface features programmable
bus sizing; individually selectable chip selects for the
upper (UCS) memory space, lower (LCS) memory
space, all non-UCS, non-LCS and I/O memory spaces;
separate byte-write enables; and boot option from an 8-
or 16-bit device.
The integrated peripherals are controlled by 16-bit
read/write registers. The peripheral registers are
contained within an internal 1-Kbyte control block. At
reset, the base of the PCB is set to FC00h in I/O space.
The registers are physically located in the peripheral
devices they control, but they are addressed as a single
1-Kbyte block. For registers, refer to the Am186™CC/
10
to 2
26
processor clocks.
Am186™CC Communications Controller Data Sheet
CH/CU Microcontrollers Register Set Manual (order
#21916).
Accesses to the PCB should be performed by direct
processor actions. The use of DMA to write or read
from the PCB results in unpredictable behavior, except
where explicit exception is made to suppor t a
peripheral function, such as the High-Speed UART
transmit and receive data registers.
The 80C186 and 80C188 microcontrollers use a
multiplexed address and data (AD) bus. The address is
present on the AD bus only during the t
The Am186CC microcontroller continues to provide the
multiplexed AD bus and, in addition, provide a
nonmultiplexed address (A) bus. The A bus provides an
address to the system for the complete bus cycle (t
t
the t
t
undefined during a refresh cycle.
The nonmultiplexed address bus (A19–A0) is valid one-
half CLKOUT cycle in advance of the address on the
AD bus. When used with the modified UCS and LCS
outputs and the byte write enable signals, the A19–A0
bus provides a seamless interface to SRAM, DRAM,
and Flash/EPROM memory systems.
For systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus on the Am186CC microcontroller during the
normal address portion of the bus cycle for accesses to
upper (UCS) and/or lower (LCS) address spaces. In
this mode, the affected bus is placed in a high-
impedance state during the address portion of the bus
cycle. This feature is enabled through the DA bits in the
Upper Memor y Chip Select (UMCS) and Lower
Memory Chip Select (LMCS) registers.
When address disable is in effect, the number of
signals that assert on the bus during all normal bus
cycles to the associated address space is reduced,
thus decreasing power consumption, reducing
processor switching noise, and preventing bus
contention with memory devices and peripherals when
operating at high clock rates.
If the ADEN pin is asserted during processor reset, the
value of the DA bits in the UMCS and LMCS registers is
ignored and the address is driven on the AD bus for all
accesses, thus preserving the industry-standard 80C186
and 80C188 microcontrollers’ multiplexed address bus
and providing support for existing emulation tools. For
r e g i s t e r s, r e f e r t o t h e A m 1 8 6 ™ C C /C H / C U
Microcontrollers Register Set Manual (order #21916).
Figure 3 on page 35 shows the affected signals during
a normal read or write operation. The address and data
are multiplexed onto the AD bus.
4
3
). During refresh cycles, the AD bus is driven during
, and t
1
phase and the values are unknown during the t
4
phases. The value driven on the A bus is
1
clock phase.
33
1
2
–
,