PL133-67 PhaseLink Corp., PL133-67 Datasheet - Page 2

• Manufacturer Part Number: PL133-67
• Description: Low-power 2.25v To 3.63v Dc To 150mhz 1 6 Fanout Buffer Ic
• Manufacturer: PhaseLink Corp.

PIN DESCRIPTIONS
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB d esign:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
- Long trace = Transmission Line. Without proper termi-
- Design long traces (> 1 inch) as “striplines” or “micro-
- Match trace at one side to avoid reflections bouncing
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REF
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
VDD
GND
OE
DNC
ringing!
nation this will cause reflections ( looks like ringing ).
strips” with defined impedance.
back and forth.
( Typical buffer impedance 20 ohm)
Name
CMOS Output Buffer
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
Place Series Resistor as close as possible to CMOS output
Connect a 33 ohm series resistor at each of the output clocks to
TSSOP-16L
2, 8, 15, 16
5, 9, 12
4, 13
10
11
14
1
3
6
7
8
enhance the stability of the output signal
Typical CMOS termination
Type
O
O
O
O
O
O
P
P
I
I
-
Input reference frequency.
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
Buffered clock output
VDD connection
GND connection
Output Enable Control Input with 130K
Do Not Connect
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
- Addition of a ferrite bead in series with VDD can
- Value of decoupling capacitor is frequency depen-
to the VDD pin(s) to limit noise from the power
supply
help prevent noise from other board sources
dant. Typical values to use are 0.1 F for designs
using frequencies < 50MHz and 0.01 F for de-
signs using frequencies > 50MHz.
50 ohm line
www.phaselink.com
Description
To CMOS Input
Rev 03/18/11
PL133-67
Pull-Up
Page 2