PL133-67 PhaseLink Corp., PL133-67 Datasheet

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PL133-67

Manufacturer Part Number
PL133-67
Description
Low-power 2.25v To 3.63v Dc To 150mhz 1 6 Fanout Buffer Ic
Manufacturer
PhaseLink Corp.
Datasheet
FEATURES
BLOCK DIAGRAM AND PACKAGE PINOUT
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
1:6 LVCMOS output fanout buffer for DC to 150MHz
8mA Output Drive Strength
Low power consumption for portable applications
Low input-output delay
Output-Output skew less than 250ps
Low Additive Phase Jitter of 60fs RMS
2.5V to 3.3V, ±10% operation
Operating temperature range from -40°C to 85°C
Available in 16-Pin SOP GREEN/RoHS package
REF
OE
Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
DESCRIPTION
The PL133-67 is an advanced fanout buffer design for
high performance, low-power, small form factor applica-
tions. The PL133-67 accepts a reference clock input from
DC to 150MHz and provides 6 outputs of the same fre-
quency.
The PL133-67 is offered in a TSSOP-16L package and it
offers the best phase noise, additive jitter performance,
and lowest power consumption of any comparable IC.
The PL133-67 outputs can be disabled to a high imped-
ance (tri-state) by pulling low the OE pin. When the OE pin
is high, the outputs are enabled and follow the REF input
signal. When the OE pin is left open, a pull-up resistor on
the chip will default the OE pin to logic 1 so the outputs are
enabled.
www.phaselink.com
CLK0
CLK1
CLK2
GND
DNC
VDD
REF
OE^
TSSOP-16L
1
2
3
4
5
6
7
8
Rev 03/18/11
PL133-67
16
15
14
13
12
11
10
9
DNC
DNC
CLK5
VDD
GND
CLK4
CLK3
GND
Page 1

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PL133-67 Summary of contents

Page 1

... IC. The PL133-67 outputs can be disabled to a high imped- ance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal ...

Page 2

... Value of decoupling capacitor is frequency depen- dant. Typical values to use are 0.1 F for designs using frequencies < 50MHz and 0.01 F for de- signs using frequencies > 50MHz. Typical CMOS termination 50 ohm line enhance the stability of the output signal PL133-67 Description Pull-Up To CMOS Input www.phaselink.com Rev 03/18/11 Page 2 ...

Page 3

... MIL-STD-883, Method 3015)…………..> 2000V s to reach minimum specified voltage DD (Commercial and Industrial Temperature Devices) Test Conditions [ –8 mA [2] OH 66.67MHz with unloaded outputs PL133-67 Min. Max. 2.25 3. -40 85 ― 30 ― 10 ― 5 ― 150 0.05 50 Min. Max. ...

Page 4

... Measured at 1.4V, Input is 50% Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded [2] Measured [ Test Conditions V =3.3V, Frequency=100MHz DD Offset=12KHz ~ 20MHz PL133-67 Additive Phase Jitter: REF Input PL133-67 Output 1000 10000 100000 Offset Frequency (Hz) 2 PL133-67 [3] Min. Typ. Max – ...

Page 5

... Input-Output Propagation Delay TEST CIRCUIT 0.1 F 0.1 F 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688 t 2 1.4V 2.0V 0. 1.4V OUTPUT 1.4V OUTPUT t VDD/2 INPUT VDD/2 OUTPUT t VDD OUTPUTS VDD GND GND PL133- 1.4V 2.0V 0. CLK C LOAD www.phaselink.com Rev 03/18/11 3. Page 5 ...

Page 6

... Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688 A1 e 2880 Zanker Road, San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER PL133- None=Tubes R=Tape & Reel Temperature Range C=Commercial (0°C to 70°C) I=Industrial (-40° ...

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